M-986-2A1P Ver la hoja de datos (PDF) - Clare Inc => IXYS
Número de pieza
componentes Descripción
Fabricante
M-986-2A1P Datasheet PDF : 13 Pages
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Coprocessor Interface Timing
td(R-A)
td(W-A)
ta(RD)
th(RD)
tsu(WR)
th(WR)
tw(RDL)
tw(WRL)
twr(RBLE)
Parameter
RD low to TBLF high
WR low to RBLE high
RD low to data valid
Data hold time after RD high
Data setup time prior to WR high
Data hold time after WR high
RD low-pulse duration
WR low-pulse duration
RBLE↑ to RBLE↓
Reset (RS) Timing
tdis(R)
td12
td13
tsu(R)
tw(R)
Parameter
Data bus disable time after RS
Delay time from RS↓ to high-impedance SCLK
Delay time from RS↓ to high-impedance DX1, DX0
Reset (RS) setup time prior to CLKOUT
RS pulse duration
M-986-2A1
Min
Nom
Max
Unit
-
-
75
ns
-
-
75
ns
-
-
80
ns
25
-
-
ns
30
-
-
ns
25
-
-
ns
80
-
-
ns
60
-
-
ns
-
-
1
ms
Test Conditions
RL = 825 Ω
CL = 100 pF
Min
Max
Unit
-
75
ns
-
200
ns
-
200
ns
50
-
ns
245
-
ns
CLKOUT Timing Parameters
tc(C)
tr(C)
tf(C)
td(MCC)
td 8
Parameter
CLKOUT cycle time
CLKOUT rise time
CLKOUT fall time
Delay time CLKIN↑ to CLKOUT↓
Delay time CLKOUT ↓ to data bus OUT valid
Test Conditions
RL = 825 Ω
CL = 100 pF
Min
195.27
-
-
25
-
Nom
195.31
10
8
-
-
Max
195.35
-
-
60
1/4tc(C)+75
Unit
ns
ns
ns
ns
ns
Transmitter Characteristics
Parameter
FOS
Frequency offset
TW
Twist
AS
Signal amplitude
TS
Time skew
Phi
Power due to extraneous components
Test Conditions
From nominal
High/low
Per component
Between components
-
Min
-
-
-7.40
-
-
Typ
-
-
-7.00
-
-
Max
±1
±0.5
-6.60
0
-30
Unit
Hz
dB
dBm0
ms
dB
Rev. 3
www.clare.com
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