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ML145428RP

Asynchronous–to–Synchronous and Synchronous–to–Asynchronous Converter

LANSDALE Semiconductor Inc. 

ML145428

LANSDALE Semiconductor, Inc.

CIRCUIT DESCRIPTION

The ML145428 Data Set Interface provides a means for con-

version of an asynchronous (start/stop format) data channel to

a synchronous data channel and synchronous to asynchronous

data channel conversion. Although primarily intended to facili-

tate the implementation of RS - 232 compatible asynchronous

data ports in digital telephone sets using the MC145422/26

UDLTs, this device is also useful in many applications that

require the conversion of synchronous and asynchronous data.

TRANSMIT CIRCUIT

Asynchronous data is input on the TxD pin. This data is

expected to consist of a start bit (logic low) followed by eight

or nine data bits and one or more stop bits (logic high). The

length of the data word is selected by the DL pin. The data

baud rate is selected with the BR1, BR1 and BR3 pins to

obtain the internal sampling clock. This internal sampling

clock is selected to be 16 times the baud rate at the TxD pin.

An externally supplied 16 times clock may also be used, in

which case the BR1, BR2, and BR3 pins should all be at logic

zero and the 16 times sampling clock supplied at the BC pin.

Data input at the TxD pin is stripped of start and stop bits

and is loaded into a four–word deep FIFO register. A break

condition is also recognized at the TxD pin and this informa-

tion is relayed to the synchronous channel transmitter which

codes this condition so it may be re–created at the remote

receiving device.

The synchronous channel transmitter sends one bit at a time

under control of the DC, CM and DOE pins. The synchronous

channel transmitter transmits one of three possible data pat-

terns based on whether or not the top of the Tx FIFO is full

and whether or not a break condition has been recognized by

the data stripper. When no data is available at the top of the Tx

FIFO for transmission, the synchronous data transmitter sends

a special synchronizing flag pattern (011111110). When a

break condition is detected by the data stripper and no data is

available at the top of the Tx FIFO, the break pattern

(111111110) is sent. Figure 2A depicts this operation.

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