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74VHCT02D-Q100

Quad 2-input NOR gate

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Nexperia

4. Functional diagram

74VHC02-Q100; 74VHCT02-Q100

Quad 2-input NOR gate

2 1A

3 1B

5 2A

6 2B

8 3A

9 3B

11 4A

12 4B

1Y 1

2Y 4

3Y 10

4Y 13

mna216

Fig 1. Logic symbol

2

≥1

3

1

5

≥1

6

4

8

≥1

9

10

11

≥1

12

13

001aah084

Fig 2. IEC logic symbol

5. Pinning information

5.1 Pinning

A

Y

B

mna215

Fig 3. Logic diagram (one gate)

9+&4

9+&74

< 

$ 

% 

< 

$ 

% 

*1' 

 9&&

 <

 %

 $

 <

 %

 $

DDD

Fig 4. Pin configuration SO14 and TSSOP14

9+&4

9+&74

WHUPLQDO

LQGH[DUHD

$ 

% 

< 

$ 

% 

*1'

 <

 %

 $

 <

 %

DDD

7UDQVSDUHQWWRSYLHZ

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 5. Pin configuration DHVQFN14

74VHC_VHCT02_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 15 November 2013

© Nexperia B.V. 2017. All rights reserved

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