D2761EB Ver la hoja de datos (PDF) - Maxim Integrated
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D2761EB Datasheet PDF : 24 Pages
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DS2761
POWER MODES
The DS2761 has two power modes: active and sleep. While in active mode, the DS2761 continually
measures current, voltage, and temperature to provide data to the host system and to support current
accumulation and Li+ safety monitoring. In sleep mode, the DS2761 ceases these activities. The DS2761
enters sleep mode when any of the following conditions occurs:
§ The PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than
2s (pack disconnection)
§ The voltage on VIN drops below undervoltage threshold VUV for tUVD (cell depletion)
§ The pack is disabled through the issuance of a SWAP command (SWEN bit = 1)
The DS2761 returns to active mode when any of the following occurs:
§ The PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high
(pack connection)
§ The PS pin is pulled low (power switch)
§ The voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit
set to 0
§ The pack is enabled through the issuance of a SWAP command (SWEN bit = 1)
The DS2761 defaults to sleep mode when power is first applied.
Li+ PROTECTION CIRCUITRY
During active mode, the DS2761 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2761 responses are described in the sections below and
summarized in Table 2 and Figure 3.
Table 2. Li+ PROTECTION CONDITIONS AND DS2761 RESPONSES
CONDITION
NAME
Overvoltage
Undervoltage
Overcurrent, Charge
Overcurrent, Discharge
Short Circuit
ACTIVATION
THRESHOLD DELAY RESPONSE
VIN > VOV
tOVD
CC high
VIN < VUV
VIS > VOC(2)
VIS < -VOC(2)
VSNS > VSC
tUVD
tOCD
tOCD
tSCD
CC , DC high,
Sleep Mode
CC , DC high
DC high
DC high
RELEASE
THRESHOLD
VIN < VCE, or
VIS ≤ -2mV
VPLS > VDD (1)
(charger connected)
VPLS < VDD - VTP (3)
VPLS > VDD - VTP (4)
VPLS > VDD - VTP (4)
VIS = VIS1 - VIS2. Logic high = VPLS for CC and VDD for DC . All voltages are with respect to VSS. ISNS references current
delivered from pin SNS.
1) If VDD < 2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD charges the battery and
allows VDD to exceed 2.2V.
2) For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: ISNS > IOC for
charge direction and ISNS < -IOC for discharge direction
3) With test current ITST flowing from PLS to VSS (pulldown on PLS)
4) With test current ITST flowing from VDD to PLS (pullup on PLS)
Overvoltage. If the cell voltage on VIN exceeds the overvoltage threshold, VOV, for a period longer than
overvoltage delay, tOVD, the DS2761 shuts off the external charge FET and sets the OV flag in the
protection register. When the cell voltage falls below charge enable threshold VCE, the DS2761 turns the
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