DS2196 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

DS2196

T1 Dual Framer LIU

Maxim Integrated 

Figure 1-1. T1 Dual Framer LIU

UOP0

UOP1

UOP2

UOP3

TCHBLKB/

TL IN KB

TCHCLKB

TLCLKB

sync

clock

data

clock

data

POWER

Back End Loopback

FLB B Mux

AIS & AIS-CI Generation

B8ZS Encode

Corrupt F-Bit / Payload

Insert Data From BERT

Yellow Alarm Generation

CRC Generation

F-Bit Insertion

Loop Code Generation

Clear Channel

Signaling Insertion

Per-Channel Loopback

Framer Loopback B

B8ZS Decoder

BPV Counter

Synchronizer

Alarm Detection

Loop Code Detector

CRC/Frame Error Count

Signaling Extraction

Channel Marking

SSER

SY SCL K

SFSYNC

TSERB

TCLKB

TSYNCB

RMSYNC

R CL K

RSER

RMSYNCA

R FSY N CA

R CL KA

RSERA

RBPVA

RLOSA / LOTCA

RCHCLKA/

RLCLKA

RCHBLKA/

RLINKA

RPOSIA

RCLKIA

RNEGIA

RNEGLO

RCLKLO

R PO SL O

WPS

RCL

Payload Loopback B

Payload Loopback A

Channel Marking

Signaling Extraction

CRC/Frame Error Count

Loop Code Detector

Alarm Detection

Synchronizer

BPV Counter

B8ZS Decoder

Framer Loopback A

Per-Channel Loopback

Signaling Insertion

Clear Channel

Loop Code Generation

F-Bit Insertion

CRC Generation

Yellow Alarm Generation

Insert Data From BERT

Corrupt F-Bit / Payload

B8ZS Encode

AIS & AIS-CI Generation

Remote Loopback

Jitter Attenuation

(can be placed in either transmit or receive path)

Local Loopback

Clock / Data

Recovery

Peak Detect

Filter

LIU AIS Generation

Wave Shaping

CSU Filters

Line Drivers

DS2196

RCHBLKB/

RLINKB

RCHCLKB/

RLCLKB

RLOSB / LOTCB

RBPVB

RSERB

RCLKB

R FSYN CB

RMSYNCB

TSYNCA

TSERA

TCLKA

TCHBLKA/

TLINKA

TCHCLKA/

TL CLKA

TPOSOA/

TNRZA

TCLKOA

TNEGOA/

TFSYNCA

TNEGLI

TCLKLI

TPOSLI

D0 to D7 /

AD0 to AD7

INT*

MUX

A0 to A6

ALE(AS) / A7

RD*(DS*)

W R* (R /W *)

BTS

CS*

JTCLK

JTDI

JTRST*

JTMS

JTDO

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