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DS1251YP

4096K NV SRAM with Phantom Clock

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DS1251/DS1251P

4096K NV SRAM with Phantom Clock

DESCRIPTION

The DS1251 4096K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 512k words by 8 bits) with a

built-in real-time clock. The DS1251Y has a self-contained lithium energy source and control circuitry, which constantly monitors

Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and

write protection is unconditionally enabled to prevent garbled data in both the memory and real-time clock.

The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, days, dates,

months, and years. The date at the end of the month is automatically adjusted for months with fewer than 31days, including

correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator.

PACKAGES

The DS1251 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the

crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for

connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be

mounted on top of the DS1251P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery because of the high temperatures required for solder reflow. The

PowerCap is Keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and

shipped in separate containers.

RAM READ MODE

The DS1251 executes a read cycle whenever (write enable) is inactive (high) and

(chip enable) is active (low). The

unique address specified by the 19 address inputs (A0-A18) defines which of the 512K bytes of data is to be accessed. Valid data

will be available to the eight data-output drivers within tACC (access time) after the last address input signal is stable, providing that

and (output enable) access times and states are also satisfied. If and

access times are not satisfied, then data

access must be measured from the later occurring signal ( or ) and the limiting parameter is either tCO for

or tOE for

, rather than address access.

RAM WRITE MODE

The DS1251 is in the write mode whenever the and

signals are in the active (low) state after address inputs are stable.

The latter occurring falling edge of

or will determine the start of the write cycle. The write cycle is terminated by the

earlier rising edge of

or . All address inputs must be kept valid throughout the write cycle. must return to the high

state for a minimum recovery time (tWR) before another cycle can be initiated. The control signal should be kept inactive (high)

during write cycles to avoid bus contention. However, if the output bus has been enabled ( and active) then will

disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when Vcc is greater than VPF. However, when Vcc is below

the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any

access. When Vcc falls below the battery switch point, Vso (battery supply level), device power is switched from the Vcc pin to the

backup battery. RTC operation and SRAM data are maintained from the battery until Vcc is returned to nominal levels.

The 3.3V device is fully accessible and data can be written or read only when Vcc is greater than VPF. When Vcc falls below the

power-fail point, VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is switched from Vcc to the

backup supply (VBAT) when Vcc drops below VPF. If VPF is greater than VBAT, the device power is switched from Vcc to the backup

supply (VBAT) when Vcc drops below VBAT. RTC operation and SRAM data are maintained from the battery until Vcc is returned to

nominal levels.

All control, data, and address signals must be powered down when Vcc is powered down.

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