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23A1024

1Mbit SPI Serial SRAM with SDI and SQI Interface

Microchip Technology 

23A1024/23LC1024

2.6 Write Mode Register Instruction

(WRMR)

The Write Mode Register instruction (WRMR) allows the

user to write to the bits in the MODE register as shown

in Table 2-2. This allows for setting of the Device

operating mode. Several of the bits in the MODE

register must be cleared to ‘0’. See Figure 2-8 for the

WRMR timing sequence.

FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR)

CS

SCK

SI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Data to MODE Register

0 00 00 0 01 7 6 54 3 2 10

High-Impedance

SO

2.7 Power-On State

The 23A1024/23LC1024 powers on in the following

state:

• The device is in low-power Standby mode

(CS = 1)

• A high-to-low-level transition on CS is required to

enter active state

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DS20005142C-page 11

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