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ICS85408

Low Skew, 1-to-8, Differential-to-LVDS Clock

Integrated Device Technology 

Low Skew, 1-to-8,

Differential-to-LVDS Clock

ICS85408I

DATASHEET

General Description

The ICS85408I is a low skew, high performance 1-to-8

ICS

Differential-to-LVDS Clock Distribution Chip and a

HiPerClockS™ member of the HiPerClockS™ family of High

Performance Clock Solutions from IDT. The ICS85408I

CLK, nCLK pair can accept most differential input

levels and translates them to 3.3V LVDS output levels. Utilizing Low

Voltage Differential Signaling (LVDS), the ICS85408I provides a low

power, low noise, low skew, point-to-point solution for distributing

LVDS clock signals.

Guaranteed output and part-to-part skew specifications make the

ICS85408I ideal for those applications demanding well defined

performance and repeatability.

Features

• Eight differential LVDS output pairs

• One differential clock input pair

• CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 700MHz

• Translates any differential input signal (LVPECL, LVHSTL, SSTL,

HCSL) to LVDS levels without external bias networks

• Translates any single-ended input signal to LVDS with resistor

bias on nCLK input

• Multiple output enable inputs for disabling unused outputs

in reduced fanout applications

• Additive phase jitter, RMS: 167fs (typical)

• Output skew: 50ps (maximum)

• Part-to-part skew: 550ps (maximum)

• Propagation delay: 2.4ns (maximum)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Block Diagram

OE

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

CLK

nQ3

nCLK

Q4

nQ4

Q5

nQ5

Q6

nQ6

Q7

nQ7

ICS85408BGI REVISION B JULY 2, 2009

Pin Assignment

nQ6 1

Q6 2

nQ5 3

Q5 4

nQ4 5

Q4 6

nQ3 7

Q3 8

nQ2 9

Q2 10

nQ1 11

Q1 12

24 Q7

23 nQ7

22 OE

21 GND

20 VDD

19 VDD

18 GND

17 VDD

16 CLK

15 nCLK

14 Q0

13 nQ0

ICS85408I

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

1

©2009 Integrated Device Technology, Inc.

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