Micrel
SY89322V
AC ELECTRICAL CHARACTERISTICS
VCC = +3.3V ±10% or +5.0V ±10%; RL = 50Ω to VCC – 2V, TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min Typ Max Units
fMAX
tPD
tSKEW
Maximum Toggle Frequency
Propagation Delay
IN-to-Q
Within-Device Skew
Part-to-Part Jitter
Note 4
Note 4
800 MHz
100
600
ps
100
ps
500
ps
tJitter
Cycle-to-Cycle Jitter
Total Jitter
Note 5
Note 6
2 ps(rms)
25 ps(pk-pk)
tr, tf
Output Rise/Fall Time (20% to 80%)
200
500
ps
Note 4.
Note 5.
Note 6.
Same transition at common VCC levels.
Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn–1,where T is the time between rising edges of the
output signal.
Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edge will deviate by more than
the specified peak-to-peak jitter value.
LVPECL OUTPUT INTERFACE APPLICATIONS
VCC
VCC
R1
ZO = 50Ω
R1
VCC
ZO = 50Ω
VCC —2V R2
R2
VCC = 3.3V; R1 = 130Ω, R2 = 82Ω
VCC = 5V; R1 = 83Ω, R2 = 125Ω
Figure 1a. Parallel Thevenin-
Equivalent Termination
VCC
ZO = 50Ω
VCC
ZO = 50Ω
50Ω
50Ω
VCC = 3.3V; Rpd = 50Ω
VCC = 5V; Rpd = 100Ω
VCC —2V
Rpd
C (Optional)
0.01µF
Figure 1b. Three Resistor
“Y Termination”
VCC
VCC
VCC
R1
R1
ZO = 50Ω
R3
VCC
R2 VCC —2V R2
R4
VCC —1.3V
VCC = 3.3V; R1 = 130Ω, R2 = 82Ω, R3 = 1kΩ, R4 = 1.6kΩ,
VCC = 5V; R1 = 83Ω, R2 = 125Ω, R3 = 1kΩ, R4 = 2.8kΩ,
Figure 1c. Terminating Unused I/O
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