HV3418PG-G Ver la hoja de datos (PDF) - Supertex Inc
Número de pieza
componentes Descripción
Fabricante
HV3418PG-G Datasheet PDF : 7 Pages
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HV3418
DC Electrical Characteristics (Over recommended operating conditions unless otherwise noted)
Sym Parameter
Min
Max
Units Conditions
IDD VDD supply current
IDDQ Quiescent VDD supply current
IPP High voltage supply current
IIH High-level logic input current
IIL Low-level logic input current
VOH High level output
HVOUT
DOUT
VOL Low level output
HVOUT
DOUT
VOC HVOUT clamp voltage
-
-
-
-
-
-
155
VDD - 1.0V
-
-
-
-
25
200
0.50
0.50
10
-10
-
-
25
1.0
VDD + 1.5
-1.5
mA fCLK = 12MHz, fDATA = 12MHz, LE = low
µA All VIN = 0 or VDD
mA VPP = 180V. All outputs high.
VPP = 180V. All outputs low.
µA VIH = VDD
µA VIL = 0V
V
VPP = 180V, IHVOUT = -5.0mA,
IDOUT = -100µA
V
VPP = 180V, IHVOUT = +5.0mA,
IDOUT = +100µA
V
IOL = +5.0mA
IOL = -5.0mA
AC Electrical Characteristics (For VDD = 12V. Values in parentheses are for VDD = 5.0V, VPP = 180V, TA = 25°C)
Sym Parameter
Min
Max
Units Conditions
fCLK Clock frequency
-
12 (6.0) MHz ---
tW Clock width high or low
40 (83)
-
ns ---
tSU Data set-up time before clock rises 25 (35)
-
ns ---
tH Data hold time after clock rises
10 (30)
-
ns ---
tWLE LE pulse width
62 (80)
-
ns ---
tDLE Delay time clock to LE high to low
25 (35)
-
ns ---
tSLE LE set-up time before clock rises
30 (40)
-
ns ---
tON, tOFF Time from LE to HVOUT
-
1.0 (1.5) µs CL = 20pF
tDHL Delay time clock to data high to low
-
50 (110)
ns CL = 20pF
tDLH Delay time clock to data low to high
-
75 (160)
ns CL = 20pF
tR, tF All logic inputs
-
5.0
ns ---
Notes:
1. Shift register speed can be as low as DC as long as data set-up and hold time meet the spec.
2. AC characteristics are guaranteed only under VDD = 12V and VDD = 5.0V.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
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