CDB4353 Ver la hoja de datos (PDF) - Cirrus Logic

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CDB4353

3.3 V Stereo Audio DAC with 2 VRMS Line Output

Cirrus Logic 

CS4353

LIST OF FIGURES

Figure 1.Serial Input Timing ...................................................................................................................... 10

Figure 2.Power-On Reset Threshold Sequence ....................................................................................... 11

Figure 3.Typical Connection Diagram ....................................................................................................... 13

Figure 4.Stereo Pseudo-Differential Output .............................................................................................. 14

Figure 5.I²S, up to 24-Bit Data .................................................................................................................. 16

Figure 6.Left-Justified up to 24-Bit Data .................................................................................................... 16

Figure 7.De-Emphasis Curve, Fs = 44.1 kHz ........................................................................................... 17

Figure 8.Internal Power-On Reset Circuit ................................................................................................. 17

Figure 9.Initialization and Power-Down Sequence Diagram ..................................................................... 19

Figure 10.Single-Speed Stopband Rejection ............................................................................................ 22

Figure 11.Single-Speed Transition Band .................................................................................................. 22

Figure 12.Single-Speed Transition Band (detail) ...................................................................................... 22

Figure 13.Single-Speed Passband Ripple ................................................................................................ 22

Figure 14.Double-Speed Stopband Rejection ........................................................................................... 22

Figure 15.Double-Speed Transition Band ................................................................................................. 22

Figure 16.Double-Speed Transition Band (detail) ..................................................................................... 23

Figure 17.Double-Speed Passband Ripple ............................................................................................... 23

Figure 18.Quad-Speed Stopband Rejection ............................................................................................. 23

Figure 19.Quad-Speed Transition Band ................................................................................................... 23

Figure 20.Quad-Speed Transition Band (detail) ....................................................................................... 23

Figure 21.Quad-Speed Passband Ripple ................................................................................................. 23

LIST OF TABLES

Table 1. Power-On Reset Threshold Voltages .......................................................................................... 11

Table 2. Digital I/O Pin Characteristics ..................................................................................................... 12

Table 3. CS4353 Operational Mode Auto-Detect ...................................................................................... 15

Table 4. Single-Speed Mode Standard Frequencies ................................................................................ 15

Table 5. Double-Speed Mode Standard Frequencies ............................................................................... 15

Table 6. Quad-Speed Mode Standard Frequencies ................................................................................. 15

Table 7. Digital Interface Format ............................................................................................................... 16

DS803PP1

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