CMX635 Ver la hoja de datos (PDF) - MX-COM Inc

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CMX635

ISDN Subscriber Processor

MX-COM Inc  

ISDN subscriber Processor

2.2 Pin description

Page 9 of 88

CMX635 Advance Information

Pin Name

STTxp, STTxn

STRxp, STRxn

DCL

FSC

IOMTx, IOMRx

AD[7:0]

ASel

Dtack

ALE

nWR

Description

ST bus differential transmit outputs. Upstream data in TE configuration and

Downstream data in NT configuration. The nominal amplitude is ±2.1V

differential with 280Ω load which equates to ±750mV at the ST interface when

the recommended line transformer is used. STTxp is positive with respect to

STTxn for transmission of the Frame Pulse bit.

Note: Particular care should be taken to avoid electro-static discharge

damage to these pins as the unpowered impedance requirements result in

reduced internal protection.

ST bus differential receive inputs. Downstream data in TE configuration and

Upstream data in NT configuration. The nominal expected differential pulse

amplitude is ±1.2V, which equates to ±750mV at the ST interface with

recommended components. Amplitudes down to 255mV at the ST interface

can be accommodated while signal activity above 100mV will generate a

“Wake-up” interrupt if required. Polarity need only be maintained for point to

multipoint configurations.

IOM-2 interface “terminal” mode data clock operating at a nominal frequency

1.536MHz. The DCL can be configured as an output (cmos levels) in timing

master mode or as an input (ttl levels) in timing slave mode. DCL operates at

twice the IOM bit rate and is used to sample the data on the IOM receive

input.

IOM-2 interface Frame Sync operating at a nominal frequency of 8kHz. The

FSC can be configured as an output (cmos levels) in timing master mode or

as an input (ttl levels) in timing slave mode. The rising edge of FSC defines

the start of an IOM frame and is nominally synchronous with the rising edge of

DCL.

IOM-2 interface transmit and receive data pins operating at a nominal bit rate

of 768kbps. The IOMTx pin equates to the IOM DD (Data Downstream) signal

when the CMX635 is the upstream device (TE configuration) and to the IOM

DU (Data Upstream) signal when the CMX635 is the downstream device (NT

configuration). The IOMTx pin can be configured as open drain or active cmos

level output. The direction of the IOMTx and IOMRx pins can be reversed for

certain channels in the IOM frame.

Processor interface Address/Data bus. Bi-directional cmos level input/output

bus that carries multiplexed address and data when multiplexed mode is

automatically detected by the CMX635 and data only when non-multiplexed

mode is detected.

Address Select. Asel, when asserted, selects the internal indirect address

register as the destination for non-multiplexed processor read/writes, or the

data register when de-asserted. Asel may be connected to A[0] of the non-

multiplexed processor address bus. Connect to Vss for multiplexed interface

operation.

Data Acknowledge. Active only when the Motorola style multiplexed mode

processor interface is detected. It is an open drain output that is pulled low at

the start of a processor read or write cycle and remains low until the CMX635

internal cycle is complete. The Dtack signal can be used to implement a

hardware handshake cycle timing mechanism.

Address Latch Enable. The multiplexed address from the AD bus is latched on

the falling edge of ALE. Connect ALE to Vcc if an Intel style non-multiplexed

interface is being used and to Vss for a Motorola style non-multiplexed

interface.

Write Strobe, active low. Latches the data from the AD bus on the rising edge

in Intel style mode. Acts as a R/nW strobe in Motorola mode. See the timing

diagrams in section 7.1 for more details on the nWR pin function.

2001 MX-COM, Inc.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480225.002

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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