CS1610A Ver la hoja de datos (PDF) - Cirrus Logic

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Fabricante

CS1610A

TRIAC Dimmable LED Driver IC

Cirrus Logic 

CS1610A/11A

CS1612A/13A

Parameter

Condition

Symbol

Min

Typ

Max Unit

Second Stage Zero-current Detect

FBZCD Threshold

FBZCD Blanking

CS1610A / 12A

CS1611A / 13A

VFBZCD(th)

-

200

-

mV

tFBZCB

-

2

-

s

-

2.8

-

s

ZCD Sink Current

FBAUX Upper Voltage

(Note 3)

IZCD = 1mA

IZCD

-2

-

-

mA

-

VDD + 0.6

-

V

Second Stage Pulse Width Modulator

Minimum On Time

-

0.55

-

s

Maximum On Time

CS1610A / 11A / 13A

CS1612A

-

8.8

-

s

-

12.0

-

s

Minimum Switching Frequency

Maximum Switching Frequency

(Note 4)

tFB(Min)

tFB(Max)

-

625

-

Hz

-

200

-

kHz

Second Stage Gate Driver

Output Source Resistance

Output Sink Resistance

Rise Time

Fall Time

CL = 0.25nF

CL = 0.25nF

ZOUT

ZOUT

-

20.3

-



-

9.4

-



-

-

30

ns

-

-

20

ns

Second Stage Protection

Overcurrent Protection (OCP)

Overvoltage Protection (OVP)

Open Loop Protection (OLP)

VOCP(th)

-

1.69

-

V

VOVP(th)

-

1.25

-

V

VOLP(th)

-

200

-

mV

External Overtemperature Protection (eOTP), Boost Peak Current, Second Stage Frequency Gain

Pull-up Current Source – Maximum

Conductance Accuracy

(Note 5)

ICONNECT

-

-

80

-

A

-

±5



Conductance Offset

(Note 5)

-

± 250

-

nS

Current Source Voltage Threshold

VCONNECT(th)

-

1.25

-

V

Internal Overtemperature Protection (iOTP)

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

(Note 6)

(Note 6)

TSD

TSD(Hy)

-

143

-

ºC

-

12

-

ºC

Notes:

1.

The CS1610A/11A/12A/13A has an internal shunt regulator that

voltage, is defined in the VDD Supply Voltage section on page 4.

limits

the

voltage

on

the

VDD

pin.

VZ,

the

shunt

regulation

2. For test purposes, load capacitance CL is connected to pin GD and is equal to 0.25nF.

3. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased

does not exceed specification.

4. Switching period (T1T2)  5 s. Period T1 and T2 are defined in the Control Parameters section on page 12.

5. The conductance is specified in Siemens (S or 1/). Each LSB of the internal ADC corresponds to 250nS or one parallel 4M

resistor. Full scale corresponds to 256 parallel 4M resistors or 15.625k.

6. Specifications are guaranteed by design and are characterized and correlated using statistical process methods.

DS976PP4

5

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