VG36128161BT Ver la hoja de datos (PDF) - Vanguard International Semiconductor
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Fabricante
VG36128161BT Datasheet PDF : 68 Pages
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
CLK cycle time
CLK to valid output delay
CLK high pulse width
CLK low pulse width
Input setup time (all input)
Input hold time (all input)
Output data hold time
CLK to output in low - Z
CLK to output in H - Z
ROW cycle time
ROW active time
RAS to CAS delay
Row precharge time
Row active to active delay
Write recovery time
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tIS
tIH
tOH3
tOH2
tLZ
tHZ
tRC
tRAS
tRCD
tRP
tRRD
tWR
tT
tRSC
tPDE
tSRX
tREF
-7H
Min
Max
7.5
7.5
5.4
5.4
2.5
2.5
1.5
0.8
2.7
2.7
0
2.7
5.4
67.5
45
100K
15
15
14
14
1
10
14
7
7
64
Limits
-7L
Min
Max
7.5
10
5.4
6
2.5
2.5
1.5
0.8
2.7
3
0
2.7
5.4
67.5
45
100K
20
20
15
15
1
10
15
7.5
7.5
64
-8H
Unit
Min
Max
10
ns
8
ns
6
ns
6
ns
3
ns
3
ns
2
ns
1
ns
3
ns
3
ns
0
ns
3
6
ns
70
ns
50
100K ns
20
ns
20
ns
20
ns
20
ns
1
10
ns
20
ns
10
ns
10
ns
64
ms
Document :1G5-0183
Rev.1
Page 8
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