CM1231-02SO(2011) Ver la hoja de datos (PDF) - ON Semiconductor
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CM1231-02SO Datasheet PDF : 12 Pages
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ESD Strike
CM1231−02SO
I/O Connector
1W
ESD
Protection
Stage 1
ESD
Protection
Stage 2
ASIC
ISHUNT1
ISHUNT2
IRESIDUAL
Figure 2. Dual Clamp ESD Protection Block Diagram
CM1231−02SO ARCHITECTURE OVERVIEW
The PicoGuard XPt two−stage per channel matched
clamp architecture with isolated clamp rails features a series
element to radically reduce the residual ESD current (IRES)
that enters the ASIC under protection (see Figure 3). From
stage 1 to stage 2, the signal lines go through matched dual
1 W resistors.
The function of the series element (dual 1 W resistors for
the CM1231−02SO) is to optimize the operation of the stage
two diodes to reduce the final IRES current to a minimum
while maintaining an acceptable insertion impedance that is
negligible for the associated signaling levels.
Each stage consists of a traditional low−cap Dual Rail
Clamp structure which steer the positive or negative ESD
current pulse to either the positive (VP) or negative (VN)
supply rail.
A zener diode is embedded between VP and VN, offering
two advantages. First, it protects the VCC rail against ESD
strikes. Second, it eliminates the need for an additional
bypass capacitor to shunt the positive ESD strikes to ground.
The CM1231−02SO therefore replaces as many as seven
discrete components, while taking advantage of precision
internal component matching for improved signal integrity,
which is not otherwise possible with discrete components at
the system level.
VP
Positive Supply Rail
VCC
IESD
1W
IRESIDUAL
Circuitry
Under
Protection
VN
Ground Rail
Figure 3. CM1231−02SO Block Diagram (IESD Flow During a Positive Strike)
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