CM1231-02SO(2011) Ver la hoja de datos (PDF) - ON Semiconductor

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CM1231-02SO
(Rev.:2011)

2, 4 and 8-Channel Low-Capacitance ESD Protection Array

ON Semiconductor 

CM1231−02SO

SINGLE AND DUAL CLAMP ESD PROTECTION

The following sections describe the standard single clamp ESD protection device and the dual clamp ESD protection

architecture of the CM1231−02SO.

Single Clamp ESD Protection

Conceptually, an ESD protection device performs the following actions upon a strike of ESD discharge into the protected

ASIC (see Figure 1).

1. When an ESD potential is applied to the system

under test (contact or air−discharge), Kirchoff’s

Current Law (KCL) dictates that the Electrical

Overstress (EOS) currents will immediately divide

throughout the circuit, based on the dynamic

impedance of each path

2. Ideally, the classic shunt ESD clamp will switch

within 1 ns to a low−impedance path and return the

majority of the EOS current to the chassis

shield/reference ground. In actuality, if the ESD

component’s response time (tCLAMP) is slower than

the ASIC it is protecting, or if the Dynamic

Resistance (RDYN) is not significantly lower than

the ASIC’s I/O cell circuitry, then the ASIC will have

to absorb a large amount of the EOS energy, and may

be more likely to fail.

3. Subsequent to the ESD/EOS event, both devices

must immediately return to their original

specifications, ready for an additional strike. Any

deterioration in parasitics or clamping capability

should be considered a failure, as it can affect signal

integrity or subsequent protection capability (this is

known as “multi−strike” capability.)

ESD Strike

I/O Connector

ISHUNT

ESD

Protection

Device

ASIC

IRESIDUAL

Figure 1. Single Clamp ESD Protection Block Diagram

Dual Clamp ESD Protection

In the CM1231−02SO dual clamp PicoGuard XPt

architecture, the first stage begins clamping immediately, as

it does in the single clamp case. The dramatically reduced

IRES current from stage one passes through the 1 W series

element and then gradually feeds into the stage two ESD

device (see Figure 2). The series inductive and resistive

elements further limit the current into the second stage, and

greatly attenuate the resultant peak incident pulse presented

at the ASIC side of the device.

This disconnection between the outside node and the

inside ASIC node allows the stage one clamps to turn on and

remain in the shunt mode before the ASIC begins to shunt

the reduced residual pulse. This gives the advantage to the

ESD component in the current division equation, and

dramatically reduces the residual energy that the ASIC must

dissipate.

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