CM1231-02SO(2011) Ver la hoja de datos (PDF) - ON Semiconductor

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CM1231-02SO
(Rev.:2011)

2, 4 and 8-Channel Low-Capacitance ESD Protection Array

ON Semiconductor 

CM1231−02SO

APPLICATION INFORMATION

CM1231−02SO Application and Guidelines

The CM1231−02SO has an integrated zener diode

between VP and VN (for each of the two stages). This greatly

reduces the effect of supply rail inductance L2 on VCL by

clamping VP at the breakdown voltage of the zener diode.

However, for the lowest possible VCL, especially when VP

is biased at a voltage significantly below the zener

breakdown voltage, it is recommended that a 0.22 mF

ceramic chip capacitor be connected between VP and the

ground plane.

With the CM1231−02SO, this additional bypass capacitor

is generally not required.

As a general rule, the ESD Protection Array should be

located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor

mentioned above should be as close to the VP pin of the

Protection Array as possible, with minimum PCB trace

lengths to the power supply, ground planes and between the

signal input and the ESD device to minimize stray series

inductance.

Figure 14. Typical Layout with Optional VP Cap Footprint

Additional Information

See also ON Semiconductor Application Note, “Design Considerations for ESD Protection,” in the Applications section.

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