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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

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1. Introduction

Product Description

PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-bit,

33 MHz implementation of the PCI Local Bus Specification, Revision 2.1. PI7C7100 supports only

synchronous bus transactions between devices on the primary 33 MHz bus and the secondary buses

operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode,

resulting in added increase in system performance. Concurrent bus operation off-loads and isolates

unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same

secondary PCI bus to communicate even while the primary bus is busy.

Product Features

• 32-bit Primary & two Secondary Ports run up to 33 MHz

• All three ports compliant with the PCI Local Bus

Specification, Revision 2.1

• Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.0.

- All I/O and memory commands

- Type 1 to Type 0 configuration conversion

- Type 1 to Type 1 configuration forwarding

- Type 1 configuration-write to special cycle conversion

• Concurrent primary to secondary bus operation and independent intra-secondary port

channel to reduce traffic on the primary port

• Provides internal arbitration for two sets of eight secondary bus masters

- Programmable 2-level priority arbiter

- Disable control for use of external arbiter

• Supports posted write buffers on all directions

• Three 128 byte FIFOs for delay transactions

• Three 128 byte FIFOs for posted memory transactions

• Enhanced address decoding

- 32-bit I/O address range

- 32-bit memory-mapped I/O address range

- VGA addressing and VGA palette snooping

- ISA-aware mode for legacy support in the first 64KB

of I/O address range

• Interrupt Handling

- PCI interrupts are routed through an external interrupt concentrator

• Supports system transaction ordering rules

• Hot-plug support on secondary buses

- 3-State control of output buffers

• IEEE 1149.1 JTAG interface support

• 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant

• 256-pin plastic BGA package

1

09/18/00 Rev 1.1

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