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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777

13.1 Config Register 1 .................................................................................................................................................... 55

13.2 Config Register 2 .................................................................................................................................................... 56

13.2.1 Config Register 1 or 2:Vendor ID Register (read only, bit 15-0; offset 00h) .......................................................... 57

13.2.2 Config Register 1: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 57

13.2.3 Config Register 2: Device ID Register (read only, bit 31-16; offset 00h) ............................................................... 57

13.2.4 Config Register 1: Command Register (bit 15-0; offset 04h) .................................................................................. 57

13.2.5 Config Register 2: Command Register (bit 15-0; offset 04h) .................................................................................. 58

13.2.6 Config Register 1 or 2: Status Register (for primary bus, bit 31-16; offset 04h) ..................................................... 59

13.2.7 Config Register 1 or 2: Revision ID Register (read only, bit 7-0; offset 08h) ......................................................... 60

13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 60

13.2.9 Config Register 1 or 2: Cache Line Size Register (read/write, bit 7-0; offset 0Ch) ................................................. 60

13.2.10 Config Register 1: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 60

13.2.11 Config Register 2: Primary Latency Timer Register (read/write, bit 15-8; offset 0Ch) ............................................ 60

13.2.12 Config Register 1: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 60

13.2.13 Config Register 2: Header Type Register (read only, bit 23-16; offset 0Ch) .......................................................... 60

13.2.14 Config Register 1: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 60

13.2.15 Config Register 2: Primary Bus Number Register (read/write, bit 7-0; offset 18h) ................................................. 60

13.2.16 Config Register 1 or 2: Secondary Bus Number Register (read/write, bit 15-8; offset 18h) ................................... 60

13.2.17 Config Register 1 or 2: Subordinate Bus Number Register (read/write, bit 23-16; offset 18h) ............................... 60

13.2.18 Config Register 1 or 2: Secondary Latency Timer (read/write, bit 31-24; offset 18h) ............................................ 60

13.2.19 Config Register 1 or 2: I/O Base Register (read/write, bit 7-0; offset 1Ch) ............................................................ 60

13.2.20 Config Register 1 or 2: I/O Limit Register (read/write, bit 15-8; offset 1Ch) ........................................................... 60

13.2.21 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 61

13.2.22 Config Register 1 or 2: Memory Base Register (read/write, bit 15-0; offset 20h) ................................................... 62

13.2.23 Config Register 1 or 2: Memory Limit Register (read/write, bit 31:16; offset 20h) ................................................. 62

13.2.24 Config Register 1 or 2: Prefetchable Memory Base Register (read/write, bit 15-0;offset 24h) ............................... 62

13.2.25 Config Register 1 or 2: Prefetchable Memory Limit Register (read/write, bit 31-16; offset 24h) ............................ 62

13.2.26 Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (read/write, bit 15-0; offset 30h) ...................... 62

13.2.27 Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (read/write, bit 31-16; offset 30h) .................... 62

13.2.28 Config Register 1 or 2: Subsystem Vendor ID (read/write, bit 15-0; offset 34h) .................................................... 62

13.2.29 Config Register 1 or 2: Subsystem ID (read/write, bit 31-16; offset 34h) ............................................................... 62

13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) ..................................................... 62

13.2.31 Config Register 1 or 2: Bridge Control Register (bit 31-16; offset 3Ch) ................................................................. 63

13.2.32 Config Register 1 or 2: Diagnostic/Chip Control Register (bit 15-0; offset 40h) .................................................... 64

13.2.33 Config Register 1 or 2: Arbiter Control Register (bit 31-16; offset 40h) ................................................................. 64

13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65

13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h) ..................... 65

13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 65

13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h) .................... 65

13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h) ...................................................... 65

13.2.39 Config Register 1: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 66

13.2.40 Config Register 2: Secondary Clock Control Register (bit 15-0; offset 68h) .......................................................... 66

13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h) .............................. 67

13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h) ............................. 67

13.2.43 Config Register 1: Port Option Register (bit 15-0; offset 74h) ............................................................................... 67

13.2.44 Config Register 2: Port Option Register (bit 15-0; offset 74h) ............................................................................... 68

13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) ................................ 69

13.2.46 Config Register 1 or 2: Retry Counter Register (read/write, bit 31-0; offset 78h) .................................................. 69

13.2.47 Config Register 1 or 2: Sampling Timer Register (read/write, bit 31-0; offset 7Ch) ................................................ 69

13.2.48 Config Register 1 or 2: Successful I/O Read Count Register (read/write, bit 31-0; offset 80h) ............................. 69

v

09/18/00 Rev 1.1

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