PI7C7100CNA Ver la hoja de datos (PDF) - Pericom Semiconductor Corporation

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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777888999000111222333444555666777888999000111222333444555666777888999000111222111222333444555666777

Table of Contents

1.

2.

3.

3.1

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.3

4.

4.1

4.2

4.3

4.4

4.5

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.5.6

4.6

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

4.6.6

4.7

4.7.1

4.7.2

4.7.3

4.7.4

4.8

4.8.1

4.8.2

4.8.3

4.8.3.1

4.8.3.2

4.8.3.3

4.8.4

4.8.4.1

4.8.4.2

Introduction/ProductFeatures ............................................................................................................................... 1

PI7C7100 Block Diagram ...................................................................................................................................... 3

Signal Definitions ................................................................................................................................................... 4

Signal Types ............................................................................................................................................................ 4

Signals ...................................................................................................................................................................... 4

Primary Bus Interface Signals .................................................................................................................................. 4

Secondary Bus Interface Signals ............................................................................................................................. 6

Clock Signals ............................................................................................................................................................ 8

Miscellaneous Signals ............................................................................................................................................. 8

JTAG Boundary Scan Signals .................................................................................................................................. 9

Power and Ground .................................................................................................................................................... 9

PI7C7100 PBGA Pin Listing ..................................................................................................................................... 9

PCI Bus Operation ................................................................................................................................................ 13

Types of Transactions ........................................................................................................................................... 13

Single Address Phase ............................................................................................................................................ 14

Device Select (DEVSEL#) Generation .................................................................................................................... 14

Data Phase ............................................................................................................................................................. 14

Write Transactions ................................................................................................................................................ 14

Posted Write Transactions .................................................................................................................................... 14

Memory Write and Invalidate Transactions .......................................................................................................... 15

Delayed Write Transactions .................................................................................................................................. 15

Write Transaction Address Boundaries ................................................................................................................ 16

Buffering Multiple Write Transactions .................................................................................................................. 16

Fast Back-to-Back Write Transactions .................................................................................................................. 16

Read Transactions ................................................................................................................................................. 17

Prefetchable Read Transactions ............................................................................................................................ 17

Non-prefetchable Read Transactions .................................................................................................................... 17

Read Pre-fetch Address Boundaries ...................................................................................................................... 17

Delayed Read Requests ......................................................................................................................................... 18

Delayed Read Completion with Target .................................................................................................................. 18

Delayed Read Completion on Initiator Bus ........................................................................................................... 18

Configuration Transactions ................................................................................................................................... 19

Type 0 Access to PI7C7100 ................................................................................................................................... 19

Type 1 to Type 0 Conversion ................................................................................................................................ 20

Type 1 to Type 1 Forwarding ................................................................................................................................ 21

Special Cycles ........................................................................................................................................................ 22

Transaction Termination ........................................................................................................................................ 22

Master Termination Initiated by PI7C7100 ............................................................................................................ 23

Master Abort Received by PI7C7100 ..................................................................................................................... 23

Target Termination Received by PI7C7100 ............................................................................................................ 24

Delayed Write Target Termination Response ....................................................................................................... 24

Posted Write Target Termination Response ......................................................................................................... 24

Delayed Read Target Termination Response ........................................................................................................ 25

Target Termination Initiated by PI7C7100 ............................................................................................................. 26

Target Retry ........................................................................................................................................................... 26

Target Disconnect .................................................................................................................................................. 27

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09/18/00 Rev 1.1

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