HIP6601BECBZ Ver la hoja de datos (PDF) - Renesas Electronics
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HIP6601BECBZ Datasheet PDF : 14 Pages
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HIP6601B, HIP6603B, HIP6604B
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated by
the driver is approximated as:
P
=
1.05 f s w
3--
2
VU
Q
U
+
VL
QL
+ IDDQVCC
(EQ. 2)
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU and
QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to the
gate pins. The IDDQ VCC product is the quiescent power of the
driver and is typically 30mW.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip during
the refresh cycle. Expressing this power in terms of the upper
MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or its
body diode conducts and pulls the PHASE node toward GND.
While the bootstrap device conducts, a current path is formed
that refreshes the bootstrap capacitor. Since the upper gate is
driving a MOSFET, the charge removed from the bootstrap
capacitor is equivalent to the total gate charge of the MOSFET.
Therefore, the refresh power required by the bootstrap
capacitor is equivalent to the power used to charge the gate
capacitance of the MOSFET.
PREFRESH
=
1--
2
fSW
QLO
S
S
V
P
V
C
C
=
1--
2
fS
W
QU
V
U
(EQ. 3)
where QLOSS is the total charge removed from the bootstrap
capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the following
characterization. The base circuit for characterizing the drivers
for different loading profiles and frequencies is provided. CU and
CL are the upper and lower gate load capacitors. Decoupling
capacitors [0.15F] are added to the PVCC and VCC pins. The
bootstrap capacitor value is 0.01F.
In Figure 1, CU and CL values are the same and frequency is
varied from 50kHz to 2MHz. PVCC and VCC are tied together
to a +12V supply. Curves do exceed the 800mW cutoff, but
continuous operation above this point is not recommended.
Figure 2 shows the dissipation in the driver with 3nF loading on
both gates and each individually. Note the higher upper gate
power dissipation which is due to the bootstrap device refresh
cycle. Again PVCC and VCC are tied together and to a +12V
supply.
FN9072 Rev 9.00
December 10, 2015
Test Circuit
+5V OR +12V
+5V OR +12V
+12V
0.01F
0.15F
PVCC
VCC
BOOT
UGATE
PHASE
2N7002
CU
0.15F PWM
LGATE
GND
2N7002
CL
100k
1000
CU = CL = 3nF
800
600
CU = CL = 2nF
400
CU = CL = 1nF
200
CU = CL = 4nF
CU = CL = 5nF
VCC = PVCC = 12V
0
500
1000
1500
2000
FREQUENCY (kHz)
FIGURE 1. POWER DISSIPATION vs FREQUENCY
1000
VCC = PVCC = 12V
800
CU = CL = 3nF
600
400
200
CU = 3nF
CL = 0nF
CCUL
=
=
0nF
3nF
0
500
1000
1500
FREQUENCY (kHz)
FIGURE 2. 3nF LOADING PROFILE
2000
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors are
varied from 1nF to 5nF. VCC and PVCC are tied together and to a
+12V supply. Figures 4, 5 and 6 show the same characterization
for the HIP6603B with a +5V supply on PVCC and VCC tied to a
+12V supply.
Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate capacitance
with upper gate capacitance held constant at three different
values. These curves apply only to the HIP6601B due to power
supply configuration.
Page 9 of 14
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