FIN1002 Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

FIN1002

LVDS 1-Bit, High-Speed Differential Receiver

Fairchild Semiconductor 

July 2016

FIN1002

LVDS 1-Bit, High-Speed Differential Receiver

Features

 Greater than 400 Mbs Data Rate

 3.3 V Power Supply Operation

 0.4 ns Maximum Pulse Skew

 2.5 ns Maximum Propagation Delay

 Bus Pin ESD (HBM) Protection Exceeds 10 kV

 Power-Off, Over-voltage tolerant Input and Output

 Fail-safe Protection for open-circuit and non-driven,

shorted, or terminated Conditions

 High-impedance Output at VCC < 1.5 V

 Meets or exceeds TIA/EIA-644 LVDS Standard

 5-Lead SOT23 Package saves Space

Description

This single receiver is designed for high-speed

interconnects utilizing Low Voltage Differential Signaling

(LVDS) technology. The receiver translates LVDS

levels, with a typical differential input threshold of

100 mV, to LVTTL signal levels. LVDS provides low EMI

at ultra low power dissipation even at high frequencies.

This device is ideal for high-speed transfer of clock or

data. The FIN1002 can be paired with its companion

driver, the FIN1001, or with any other LVDS driver.

Ordering Information

Part Number

FIN1002M5

FIN1002M5X

Operating

Temperature

Range

-40 to +125°C

-40 to +125°C

Package

Packing Method

Packing

Quantity

5-Lead SOT23, JEDEC MO-178, 1.6 mm

5-Lead SOT23, JEDEC MO-178, 1.6 mm

Tube

Tape & Reel

250

3000

Connection Diagram

© 2002 Fairchild Semiconductor Corporation

FIN1002 • Rev. 1.2

Figure 1. Top View

www.fairchildsemi.com

Share Link: