ZL30406QGG1 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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Fabricante

ZL30406QGG1

SONET/SDH Clock Multiplier PLL

Zarlink Semiconductor Inc 

ZL30406

Data Sheet

2.2 Recommended Interface Circuit

2.2.1 LVPECL to LVPECL Interface

The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at

77.76 MHz. The LVPECL output drivers require a 50 Ω termination connected to the VCC-2V source for each

output terminal at the terminating end as shown below. The terminating resistors should be placed as close as

possible to the LVPECL receiver.

+3.3 V

ZL30406

VCC

LVPECL

Driver

GND

C77oP-A

C77oN-A

0.1 uF

Z=50 Ω

Z=50 Ω

VCC=+3.3 V

R1

R1

LVPECL

Receiver

R2

R2

Typical resistor values: R1 = 130 Ω, R2 =82 Ω

Figure 6 - LVPECL to LVPECL Interface

2.2.2 CML to CML Interface

The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz,

155.52 MHz selected with FS1-2 pins. The output drivers require a 50 Ω load at the terminating end if the receiver

is CML type.

+3.3 V

ZL30406

VCC

0.1 uF

CML

Driver

GND

OC-CLKoP 0.1 uF Z=50 Ω

OC-CLKoN

0.1 uF

Z=50 Ω

Low Impedance

DC bias source

50 Ω

50 Ω

CML

Receiver

Figure 7 - CML to CML Interface

9

Zarlink Semiconductor Inc.

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