ZL30406QGG1 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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ZL30406QGG1

SONET/SDH Clock Multiplier PLL

Zarlink Semiconductor Inc 

ZL30406

Data Sheet

2.3 Tristating LVPECL Outputs

The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-

12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required,

a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When

disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.

For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be

used as shown in Figure 10. Typically this might be required in hot swappable applications.

Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC

coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to

the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6

are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the

LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,

R5 and R6 should not be populated.

C77oEN

ZL30406

C1

0.1 u

Z=50

3.3 V 3.3 V

R3 R5

127 127

C2

R1 R2 0.1 u

200 200

Z=50

R4 R6

82.5 82.5

Figure 10 - Tristatable LVPECL Outputs

11

Zarlink Semiconductor Inc.

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