ZL30415GGG2 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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Fabricante

ZL30415GGG2

SONET/SDH Clock Multiplier PLL

Zarlink Semiconductor Inc 

ZL30415

Data Sheet

2.6 Frequency Dividers and Clock Drivers

The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to

provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o

output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball.

Internally, this block provides a feedback clock that closes the PLL loop.

The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the

following table.

OC-CLKo

FS3

FS2

FS1

Frequency

0

0

0

19.44 MHz

0

0

1

38.88 MHz

0

1

0

77.76 MHz

0

1

1

155.52 MHz

1

0

0

622.08 MHz

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

Table 2 - OC-CLKo Clock Frequency Selection

6

Zarlink Semiconductor Inc.

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