SC1453ISK32TRT Ver la hoja de datos (PDF) - Semtech Corporation
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SC1453ISK32TRT Datasheet PDF : 14 Pages
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SC1453
POWER MANAGEMENT
Applications Information (Cont.)
Inserting these values into equation (2) gives us:
Layout Considerations
PD(MAX) = (3.465 − 2.744)• 0.150 = 108mW
Using this figure, we can calculate the maximum thermal
impedance allowable to maintain TJ ≤ 125°C:
( ) ( ) θJA(MAX) =
TJ(MAX) − TA(MAX)
PD(MAX )
=
125 − 85
0.108
= 370°C / W
While layout for linear devices is generally not as critical
as for a switching application, careful attention to detail
will ensure reliable operation.
1) Attaching the part to a larger copper footprint will
enable better heat transfer from the device, especially
on PCBs where there are internal ground and power
planes.
With the standard SOT-23-5/TSOT-23-5 Land Pattern
shown at the end of this datasheet, and minimum trace
widths, the thermal impedance junction to ambient for
SC1453ISK is 256°C/W. Thus no additional heatsinking
is required for this example.
The junction temperature can be reduced further (or
higher power dissipation can be allowed) by the use of
larger trace widths and connecting PCB copper to the
GND pin (pin 2), which connects directly to the device
substrate. Adding approximately one square inch of PCB
copper to pin 2 will reduce θJA to approximately
130°C/W and T
for the example above to
J(MAX)
approximately 100°C for the SOT-23-5 package. The use
of multi layer boards with internal ground/power planes
will lower the junction temperature and improve overall
output voltage accuracy.
2) Place the input, output and bypass capacitors close
to the device for optimal transient response and device
behaviour.
3) Connect all ground connections directly to the ground
plane. If there is no ground plane, connect to a common
local ground point before connecting to board ground.
2006 Semtech Corp.
7
www.semtech.com
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