EM78860 Ver la hoja de datos (PDF) - ELAN Microelectronics
Número de pieza
componentes Descripción
Fabricante
EM78860 Datasheet PDF : 25 Pages
| |||
EM78860
8-BIT MICRO-CONTROLLER
It is very important to save ACC,R3 and R5 when processing a interruption.
Address
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
:
:
:
:
:
:
:
:
Instruction
DISI
MOV A_BUFFER,A
SWAP A_BUFFER
SWAPA 0x03
MOV R3_BUFFER,A
MOV A,0x05
MOV R5_BUFFER,A
:
:
MOV A,R5_BUFFER
MOV 0X05,A
SWAPA R3_BUFFER
MOV 0X03,A
SWAPA A_BUFFER
RETI
Note
;Disable interrupt
;Save ACC
;Save R3 status
;Save ROM page register
;Return R5
;Return R3
;Return ACC
Instruction Set
Instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register.
The symbol “R” represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. “b’’ represents a bit field designator which selects the number of the
bit, located in the register “R’’, affected by the operation. “k’’ represents an 8 or 10-bit constant or literal
value.
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0014
001r
0020
00rr
0080
00rr
01rr
01rr
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
TBL
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
OPERATION
STATUS
AFFECTED
No Operation
None
Decimal Adjust A
C
A CONT
None
0 WDT, Stop oscillator
T,P
0 WDT
T,P
A IOCR
None
Enable Interrupt
None
Disable Interrupt
None
[Top of Stack] PC
None
[Top of Stack] PC
Enable Interrupt
None
CONT A
None
IOCR A
None
R2+A R2 bits 9,10 do not clear Z,C,DC
AR
None
0A
Z
0R
Z
R-A A
Z,C,DC
R-A R
Z,C,DC
* This specification are subject to be changed without notice.
6.24.1998 16
Share Link: 