EM78860
8-BIT MICRO-CONTROLLER
TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC
only or WDT only at the same time.
• An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT
register.
• See the prescaler ratio in CONT register.
• Fig. 10 depicts the circuit diagram of TCC/WDT.
• Both TCC and prescaler will be cleared by instructions which write to TCC each time.
• The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
• The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
CLK(=Fosc/2)
Data Bus
TCC
(32K CLK)
0
M
1
U
X
1
M
0
U
X
SYNC
2 cycle
TCC(R1)
TE
TS
PAB
TCC overflow interrupt
WDT
WDTE
0
M
U
1
X
PAB
8-bit Counter
8-to-1 MUX
MUX
PSR0~PSR2
PAB
WDT timeout
Fig. 10 Block diagram of TCC WDT
I/O Ports
The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by
software control. The I/O ports can be defined as “input” or “output” pins by the I/O control registers (IOC6 ~
IOC9 ) under program control. The I/O registers and I/O control registers are both readable and writable. The
I/O interface circuit is shown in Fig.11.
* This specification are subject to be changed without notice.
6.24.1998 13