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ICS844256D

FemtoClock® Crystal-to-LVDS Frequency Synthesizer w/Integrated Fanout Buffer

Integrated Device Technology 

ICS844256D Data Sheet

FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER

Table 1. Pin Descriptions

Number

1, 2

3, 4

5, 6

Name

VDDO

nQ2, Q2

nQ1, Q1

Type

Power

Output

Output

Description

Output supply pins.

Differential output pair. LVDS interface levels.

Differential output pair. LVDS interface levels.

7, 8

nQ0, Q0

Output

Differential output pair. LVDS interface levels.

9

10

11

12

13,

14

15,

18

16, 17

19, 20

21, 22

23, 24

PLL_BYPASS

VDDA

VDD

FB_SEL

XTAL_IN,

XTAL_OUT

N_SEL0,

N_SEL1

GND

nQ5, Q5

nQ4, Q4

nQ3, Q3

Input

Power

Power

Input

Input

Input

Power

Output

Output

Output

Pullup

Pulldown

PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH,

the PLL is bypassed and the output frequency = crystal frequency ÷ N output

divider. LVCMOS / LVTTL interface levels.

Analog supply pin.

Core supply pin.

Feedback and output frequency select pin. LVCMOS/LVTTL interface levels.

See Table 3.

Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

Pullup

Feedback and output frequency select pins. LVCMOS/LVTTL interface levels.

See Table 3.

Power supply ground.

Differential output pair. LVDS interface levels.

Differential output pair. LVDS interface levels.

Differential output pair. LVDS interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

Parameter

CIN

Input Capacitance

RPULLUP

Input Pullup Resistor

RPULLDOWN Input Pulldown Resistor

Test Conditions

Minimum

Typical

4

51

51

Maximum

Units

pF

kΩ

kΩ

ICS844256DG REVISION A AUGUST 5, 2010

2

©2010 Integrated Device Technology, Inc.

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