SPT8100SIT Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
SPT8100SIT Datasheet PDF : 10 Pages
| |||
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ...................................................................... +6 V
DVDD ..................................................................... +6 V
OVDD ..................................................................... +6 V
Input Voltages
Analog Input ................................. –0.5 V to VDD +0.5 V
CLK Input ............................................................... VDD
AVDD – DVDD .................................................. ±100 mV
Delta between AGND, DGND, and OGND ...... ±100 mV
ELECTRICAL SPECIFICATIONS
Output
Digital Outputs .................................................... 10 mA
Temperature
Operating Temperature ........................... –40 to +85 °C
Junction Temperature ...................................... +175 °C
Lead Temperature (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions in
typical applications.
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless
otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT8100
TYP
MAX
UNITS
Resolution
15.9
16
Bits
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
Gain Error1
Offset Error2
V
±1.25
LSB
V
±0.5
LSB
IV
–7.5
+7.5
%FSR
IV
–5
+5
%FSR
Analog Input (into PGA)
Differential Input Voltage Range
VIN+, VIN–
Input Capacitance
Input Resistance3
PGA Gain = 0 dB
Input Bandwidth4
PGA Gain = 0 dB
Input Common Mode Voltage Range
V
5
VPPD
IV
15
pF
IV
5.5
kΩ
V
12
MHz
V
1.15
2.40
3.65
V
Programmable Gain Amp
Composite Input-Referred
ƒIN > 300 kHz
Noise Floor
PGA Gain = 0 dB
V
PGA Gain = 2.9 dB
V
PGA Gain = 5.8 dB
V
PGA Gain = 11.8 dB
V
PGA Gain = 14.8 dB
V
PGA Gain = 17.5 dB
V
PGA Gain = 19.5 dB
V
PGA Range
V
PGA Gain Steps3
VI
PGA Gain Accuracy
VI
1.4
1.5
1.6
2.0
2.3
2.6
2.8
19.5
0,2.9,5.8,11.8,14.8,17.5,19.5
±0.3
LSBRMS
LSBRMS
LSBRMS
LSBRMS
LSBRMS
LSBRMS
LSBRMS
dB
dB
dB
Conversion Characteristics
Maximum Conversion Rate
Pipeline Delay (Latency)5
Reset Pulse Time (RS)
Reset Calibration Time
FS = 5 MSPS
VI
5
IV
IV
3
V
MSPS
5.5
Clocks
Clocks
150
ms
References and External Bias
VRT – VRB (Internal Ref)
Bias Resistor Range (External)
VCM Output Voltage
VCM Output Current
VRT
VRB
1 Total gain error of PGA and ADC using internal references.
2 Total offset error of PGA and ADC relative to mid-scale.
3 See table I for input resistance as a function of PGA gain.
VI
2.375
2.5
2.625
V
V
800
1430
2500
Ω
IV
2.275
2.40
2.525
V
IV
47
µA
V
3.45
3.65
3.85
V
V
0.95
1.15
1.35
V
4 Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
5 The input is sampled on the falling edge of the clock and is available on the
output after the rising edge of the clock, 5.5 clock cycles later.
SPT8100
2
1/9/02
Share Link: 