SPT8100SIT Ver la hoja de datos (PDF) - Cadeka Microcircuits LLC.
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Fabricante
SPT8100SIT Datasheet PDF : 10 Pages
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Figure 5 – Timing Diagram 2
CLK
tD1
Digital
Outputs
OE
tD2
tD3
FFT Plot
Table II – Timing Parameters
Parameter
Symbol Min Typ Max
CLK high to Data Valid
tD1
18 24 401
OE inactive to HiZ
tD2
10 16 30
OE active to Data Valid tD3
10 16 30
1 Conditions: load capacitance = 20 pF, VOH = 3.3 V
Units
ns
ns
ns
Typical Differential Linearity Error (DLE)
Test Conditions:
ƒIN = 2 MHz
ƒCLK = 4.4 MHz
PGA Gain = 18 dB
REXT = 1.08 kΩ
ADC Input (Post PGA) = –5.4 dBFS
TA = +25 °C
Test Conditions:
ƒIN = 75 kHz
ƒCLK = 4.4 MHz
PGA Gain = 0 dB
Near Full-Scale Input
Two-Tone Intermodulation FFT
Spurious-Free Dynamic Range
100
95
90
0.9 MHz, low
0.9 MHz, med
0.9 MHz, high
85
80
2 MHz, high
75
2 MHz, med
70
2 MHz, low
65
3 MHz, high
60
Test Conditions:
ƒ1 = 890 kHz
ƒ2 = 900 kHz
ƒCLK = 4.4 MHz
PGA Gain = 6 dB
REXT = 1.43 kΩ
ADC Input (Post PGA) = –8.0 dBFS
TA = +25 °C
55
3 MHz, med
50
45
–10
3 MHz, low
–9 –8 –7 –6 –5 –4 –3 –2 –1 0
Composite Level at ADC Input (dBFS) 5 VP-P
Test Conditions:
10 MSPS, 5 V, 25 °C
Med: REXT=1.24 kΩ @109 mA
Low: REXT=1.43 kΩ @96 mA High: REXT=1 kΩ @129 mA
SPT8100
8
1/9/02
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