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SPT8100SIT

16-BIT, 5 MSPS CMOS A/D CONVERTER

Cadeka Microcircuits LLC. 

Figure 3 – Timing Diagram 1

Analog In

n+1

n+2

n

n+3

n+4

n+8

n+5

n+6

n+7

CLK

tD

D0–D15

OVR

n

n+1

n+2

INPUT/OUTPUT TIMING

OUTPUT ENABLE

The SPT8100 implements a simple interface: the 16 ADC

outputs appear on the pins D15–D0 as a parallel word syn-

chronous with the ADC sampling clock. D0 is the LSB and

D15 is the MSB. The timing diagram for the ADC digital

outputs is shown in figure 3. The data is sampled at the fall-

ing edge of the clock. The ADC sampling clock is at the

same frequency as CLK.

The output data is updated on the rising edge of CLK with

a clock latency of 5.5 clock cycles.

OUTPUT LOGIC LEVEL

The voltage levels on the D15–D0 lines and OVR are

CMOS levels: the HIGH level is determined by the power

supply voltage on the OVDD pin, which can be set indepen-

dently of the other supply pins on the device over the range

from 3.0 V to 5.25 V (3.3 V typical). The RDY pin level is

determined by DVDD (+5 V).The external digital output

buffers should be placed as close as possible to the

SPT8100 digital outputs to minimize any line reflections

that would cause performance degradation.

ADC REFERENCES

The ADC full-scale range is set by reference voltages gen-

erated on chip. These two reference voltages appear on

pins VRT and VRB; nominally their difference is 2.5 V. The

references are not designed to be overdriven. The VRT and

VRB pins should be very carefully decoupled on the board

using as short a trace as possible. Some optimization of

the decoupling may be required, as shown in the typical

interface circuit diagram. The smallest capacitor should be

the closest one to the chip. (Refer to the typical interface

circuit diagram.)

The ADC digital outputs are enabled by the active high

output enable pin (OE).

OE = 1: ADC digital outputs are enabled

OE = 0: ADC digital outputs are high-impedance

(tri-stated)

DIGITAL CODE RANGE AND

OUT-OF-RANGE DETECTION

The output format of the ADC digital data is offset binary.

Due to the calibration algorithm used, there is a slight loss

in digital code range from the ADC. Instead of FFFFH and

0000H at the extremes of the range, the actual maximum

and minimum codes are less than that by 1.6% at both

ends of the scale, and vary from chip to chip. Effectively,

this is a loss in dynamic range of a few tenths of a dB, and

is negligible in many applications. The out-of-range func-

tion is defined accordingly, and sets the state of the active

high digital output OVR, as follows:

OVR is HIGH if the ADC digital code is greater

than or equal to FC00H or less than or equal to

03FFH. (See figure 4.)

If the output code exceeds FC00(max) or 03FF(min), this

implies that output is clipping. Therefore, once these limits

are crossed, the second harmonic becomes significant

and degrades performance.

Figure 4 – ADC Digital Code Range and Overrange

Bit Function

FFFFH

FC00H

OVR = 1

65535

1.6% FSR

64512

ADC

Digital Code

Range

OVR = Ø

03FFH

0000H

OVR = 1

1023

1.6% FSR

0

SPT8100

7

1/9/02

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