SPT8100SIT Ver la hoja de datos (PDF) - Cadeka Microcircuits LLC.
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SPT8100SIT Datasheet PDF : 10 Pages
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless
otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT8100
TYP
MAX
UNITS
Dynamic Performance1
Effective Number of Bits
ADC Input = –1 dBFS2
ƒIN = 60 kHz
IV
ƒIN = 900 kHz
V
Signal-to-Noise Ratio
(without Harmonics)
ADC Input = –1 dBFS2
ƒIN = 75 kHz
IV
ƒIN = 900 kHz
Harmonic Distortion
V
ADC Input = –0.5 dBFS
ƒIN = 60 kHz
IV
ƒIN = 900 kHz
V
Signal-to-Noise and Distortion
(SINAD)
ADC Input = –1 dBFS
ƒIN = 60 kHz
IV
ƒIN = 900 kHz
V
Spurious Free Dynamic Range3
ƒIN = 60 kHz
ADC Input = –0.5 dB
IV
ƒIN = 900 kHz
ƒIN = 2 MHz
ƒIN = 3 MHz
Two-Tone Intermodulation
V
REXT = 1 kΩ @ 10 MSPS
V
REXT = 1 kΩ @ 10 MSPS
V
3rd Order Distortion
ƒ1=400 kHz, ƒ2=410 kHz4 V
ƒ1=890 kHz, ƒ2=900 kHz5 V
12.2
78
75
85
13.0
12.7
81
80
–92
–82
80
78
94
94
83
78
–94
–89
Bits
Bits
dB
dB
–84
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dB
dB
Inputs
GS0–GS2 Logic 1 Voltage
GS0–GS2 Logic 0 Voltage
CLK, RS Logic 1 Voltage
CLK, RS Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
2.4
V
VI
0.8
V
VI
2.0
V
VI
0.8
V
VI
–10
+10
µA
VI
–10
+10
µA
V
5
pF
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
CLK to Output Delay Time (tD)
IOH = –2 mA
IOL = 2 mA
CLOAD = 20 pF
VI OVDD – 0.5
VI
IV
V
0.4
V
30
ns
Power Supply Requirements
Voltages OVDD
AVDD
DVDD
Currents IDD
Power Dissipation
1 Dynamic performance tested at ƒS=4.4 MSPS
2 0 dBFS is 5.0 V peak-to-peak differential
3 ADC Input = –8.1 dBFS, unless otherwise noted
IV
3.0
3.3
5.25
V
IV
4.75
5.0
5.25
V
IV
4.75
5.0
5.25
V
VI
93
103
mA
VI
465
515
mW
4 Test Conditions: PGA setting of 5.8 dB; Analog Input at ADC = –0.7 dB
5 Test Conditions: PGA setting of 0 dB; Analog Input at ADC = –1.9 dB
TEST LEVEL CODES
TEST LEVEL
All electrical characteristics are subject
I
to the following conditions:
II
All parameters having min/max specifi-
cations are guaranteed. The Test Level
III
column indicates the specific device
testing actually performed during
IV
production and Quality Assurance
inspection. Any blank section in the data
V
column indicates that the specification is
VI
not tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT8100
3
1/9/02
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