ADSP-21062CS-160 Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21062CS-160

ADSP-2106x SHARC® DSP Microcomputer Family

Analog Devices 

ADSP-21062/ADSP-21062L

PIN FUNCTION DESCRIPTIONS

ADSP-21062 pin definitions are listed below. All pins are iden-

tical on the ADSP-21062 and ADSP-21062L. Inputs identified

as synchronous (S) must meet timing requirements with respect

to CLKIN (or with respect to TCK for TMS, TDI). Inputs

identified as asynchronous (A) can be asserted asynchronously

to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND,

except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that

have internal pull-up or pull-down resistors (CPA, ACK, DTx,

DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS

and TDI)—these pins can be left floating. These pins have a

logic-level hold circuit that prevents the input from floating

internally.

A = Asynchronous G = Ground

I = Input

O = Output

P = Power Supply S = Synchronous

(A/D) = Active Drive (O/D) = Open Drain

T = Three-State (when SBTS is asserted, or when the

ADSP-21062 is a bus slave)

Pin

ADDR31-0

Type

I/O/T

DATA47-0 I/O/T

MS3-0

O/T

RD

I/O/T

WR

I/O/T

PAGE

O/T

ADRCLK

SW

O/T

I/O/T

ACK

I/O/S

Function

External Bus Address. The ADSP-21062 outputs addresses for external memory and peripherals on

these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal

memory or IOP registers of other ADSP-21062s. The ADSP-21062 inputs addresses when a host

processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.

External Bus Data. The ADSP-21062 inputs and outputs data and instructions on these pins. 32-bit

single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the

bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short

word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over

bits 23–16. Pull-up resistors on unused DATA pins are not necessary.

Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of

external memory. Memory bank size must be defined in the ADSP-21062’s system control register

(SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the

other address lines. When no external memory access is occurring the MS3-0 lines are inactive; they are

active however when a conditional memory access instruction is executed, whether or not the condi-

tion is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0).

In a multiprocessing system the MS3-0 lines are output by the bus master.

Memory Read Strobe. This pin is asserted (low) when the ADSP-21062 reads from external

memory devices or from the internal memory of other ADSP-21062s. External devices (including

other ADSP-21062s) must assert RD to read from the ADSP-21062’s internal memory. In a multipro-

cessing system RD is output by the bus master and is input by all other ADSP-21062s.

Memory Write Strobe. This pin is asserted (low) when the ADSP-21062 writes to external memory

devices or to the internal memory of other ADSP-21062s. External devices must assert WR to write to

the ADSP-21062’s internal memory. In a multiprocessing system WR is output by the bus master and

is input by all other ADSP-21062s.

DRAM Page Boundary. The ADSP-21062 asserts this pin to signal that an external DRAM page

boundary has been crossed. DRAM page size must be defined in the ADSP-21062’s memory control

register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can

only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.

Synchronous Write Select. This signal is used to interface the ADSP-21062 to synchronous

memory devices (including other ADSP-21062s). The ADSP-21062 asserts SW (low) to provide an

early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in

a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is

input by all other ADSP-21062s to determine if the multiprocessor memory access is a read or write.

SW is asserted at the same time as the address output. A host processor using synchronous writes

must assert this pin when writing to the ADSP-21062(s).

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external

memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off

completion of an external memory access. The ADSP-21062 deasserts ACK as an output to add wait

states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-

21062 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.

The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it

was last driven.

–8–

REV. B

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