ADSP-21062CS-160 Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21062CS-160

ADSP-2106x SHARC® DSP Microcomputer Family

Analog Devices 

ADSP-21062/ADSP-21062L

Pin

TFSx

RFSx

LxDAT3-0

Type

I/O

I/O

I/O

LxCLK

I/O

LxACK

I/O

EBOOT

I

LBOOT

I

BMS

I/O/T*

CLKIN

I

RESET

I/A

TCK

I

TMS

I/S

TDI

I/S

TDO

O

TRST

I/A

EMU

O

ICSA

O

VDD

P

GND

G

NC

Function

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor

that is enabled or disabled by the LPDRD bit of the LCOM register.

EPROM Boot Select. When EBOOT is high, the ADSP-21062 is configured for booting from an 8-

bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table

below. This signal is a system configuration selection that should be hardwired.

Link Boot. When LBOOT is high, the ADSP-21062 is configured for link port booting. When

LBOOT is low, the ADSP-21062 is configured for host processor booting or no booting. See table

below. This signal is a system configuration selection that should be hardwired.

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-

cates that no booting will occur and that ADSP-21062 will begin executing instructions from external

memory. See table below. This input is a system configuration selection that should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT LBOOT BMS

Booting Mode

1

0

0

0

0

1

0

0

0

1

1

1

Output

1 (Input)

1 (Input)

0 (Input)

0 (Input)

x (Input)

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Link Port

No Booting. Processor executes from external memory.

Reserved

Reserved

Clock In. External clock input to the ADSP-21062. The instruction cycle rate is equal to CLKIN.

CLKIN may not be halted, changed, or operated below the minimum specified frequency.

Processor Reset. Resets the ADSP-21062 to a known state and begins program execution at the

program memory location specified by the hardware reset vector address. This input must be asserted

(low) at power-up.

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up

resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal

pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-

up or held low for proper operation of the ADSP-21062. TRST has a 20 kΩ internal pull-up resistor.

Emulation Status. Must be connected to the ADSP-21062 EZ-ICE target board connector only.

Reserved, leave unconnected.

Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins)

Power Supply Return. (30 pins)

Do Not Connect. Reserved pins which must be left open and unconnected.

–10–

REV. B

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