CY22392 Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY22392

Three-PLL General Purpose FLASH Programmable Clock Generator

Cypress Semiconductor 

CY22392

associated logic, while suspending an output simply forces a can download a copy of CyClocksRT for free on Cypress’s web

three-state condition.

site at www.cypress.com.

Improving Jitter

Jitter Optimization Control is useful in mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning,

allowing superior jitter performance.

Power Supply Sequencing

For parts with multiple VDD pins, there are no power supply

sequencing requirements. The part is not be fully operational

until all VDD pins have been brought up to the voltages specified

in the “Operating Conditions” table.

All grounds must be connected to the same ground plane.

CyClocksRT™ Software

CyClocksRT is our second-generation application that allows

users to configure this device. The easy-to-use interface offers

complete control of the many features of this family including

input frequency, PLL and output frequencies, and different

functional options. Data sheet frequency range limitations are

checked and performance tuning is automatically applied.

CyClocksRT also has a power estimation feature that allows you

to see the power consumption of your specific configuration. You

Junction Temperature Limitations

It is possible to program the CY22392 such that the maximum

Junction Temperature rating is exceeded. The package θJA is

115 C/W. Use the CyClocksRT power estimation feature to verify

that the programmed configuration meets the Junction

Temperature and Package Power Dissipation maximum ratings.

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Supply Voltage................................................–0.5V to +7.0V

DC Input Voltage ........................... –0.5V to + (AVDD + 0.5V)

Storage Temperature ................................. –65°C to +125°C

Junction Temperature .................................................. 125°C

Data Retention at Tj = 125°C .................................>10 years

Maximum Programming Cycles........................................100

Package Power Dissipation...................................... 350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ..........................................

2000V

Latch up (per JEDEC 17) .................................... > ±200 mA

Operating Conditions[1]

Parameter

VDD/AVDD

TA

CLOAD_OUT

fREF

tPU

Description

Supply Voltage

Commercial Operating Temperature, Ambient

Industrial Operating Temperature, Ambient

Max. Load Capacitance

External Reference Crystal

External Reference Clock[2], Commercial

External Reference Clock[2], Industrial

Power up time for all VDD's to reach minimum specified voltage

(power ramps must be monotonic)

Min

3.135

0

–40

–

8

1

1

0.05

Typ.

3.3

–

–

–

–

–

–

–

Max

3.465

+70

+85

15

30

166

150

500

Unit

V

°C

°C

pF

MHz

MHz

MHz

ms

Notes

1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.

Document #: 38-07013 Rev. *E

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