CY22392(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY22392 Datasheet PDF : 8 Pages
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CY22392
Electrical Characteristics
Parameter
IOH
IOL
CXTAL_MIN
CXTAL_MAX
CLOAD_IN
VIH
VIL
IIH
IIL
IOZ
IDD
Description
Output High Current[3]
Output Low Current[3]
Crystal Load Capacitance[3]
Crystal Load Capacitance[3]
Input Pin Capacitance[3]
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Total Power Supply Current
Conditions
VOH = VDD – 0.5, VDD = 3.3 V
VOL = 0.5V, VDD = 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of AVDD
CMOS levels,% of AVDD
VIN = AVDD – 0.3 V
VIN = +0.3 V
Three-state outputs
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
IDDS
Total Power Supply Current in Shutdown active
Shutdown Mode
Min.
12
12
–
–
–
70%
–
–
–
–
–
–
–
Typ.
24
24
6
30
7
–
–
<1
<1
100
50
5
Max.
–
–
–
–
–
–
30%
10
10
10
–
Unit
mA
mA
pF
pF
pF
AVDD
AVDD
µA
µA
µA
mA
–
mA
20
µA
Switching Characteristics
Parameter
1/t1
t2
t3
t4
Name
Description
Output Frequency[3, 4] Clock output limit, Commercial
Clock output limit, Industrial
Output Duty Cycle[3, 5] Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2, measured at VDD/2
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1, measured at VDD/2
Rising Edge Slew Rate[3] Output clock rise time, 20% to 80% of VDD
Falling Edge Slew
Rate[3]
Output clock fall time, 20% to 80% of VDD
t5
Output three-state
Timing[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
t6
Clock Jitter[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at VDD/2
t7
Lock Time[3]
PLL Lock Time from Power-up
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Min.
–
–
45%
40%
0.75
0.75
–
–
–
Typ.
–
–
50%
50%
1.4
1.4
150
400
1.0
Max.
200
166
55%
Unit
MHz
MHz
60%
– V/ns
– V/ns
300 ns
–
ps
3
ms
Document #: 38-07013 Rev. *D
Page 5 of 8
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