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LA4571MB Ver la hoja de datos (PDF) - SANYO -> Panasonic

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LA4571MB Datasheet PDF : 9 Pages
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LA4571MB
The internal circuit of the POWER MUTE pin is shown
in the following figure.
The power amplifier input pin, POWER IN1, is biased at
1.8V, and the output pins at 1.2V
Reference Voltage
The input to the voltage reference amplifier is a
voltage divided level from the supply voltage ripple
filter. The referecne voltage is given by 0.6 × VCC.
The supply voltage ripple filter requires the connection
of an external filter capacitor to RF REF. A large
capacitance results in a high ripple rejection ratio.
Noise filtering is achieved by the addition of a single
capacitor to VREF. Since the reference voltage ampli-
fier has a buffered output, this capacitor can be as low
as 1µF.
Design Notes
The preamplifier inputs should be connected to VREF
through a 2.2kresistor if there is no tape head input
signal source.
The mute release time capacitor of the power amplifier
should be between 1.0 and 4.7µF. For VCC=3.0V and
C=2.2µF, the mute release time is 0.7s.
The ripple rejection ratio setting capacitor should be
between 2.2 and 33µF. For 2.2µF, the ripple rejection
ratio is 35dB, and for 22µF, it is 55dB.
When the output amplifier turns OFF, the protection
circuit shown in the following figure detects the falling
supply voltage and then mutes the power amplifier to
protect the device.
Sample Application Circuit
No.3534–8/9

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