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MC100EP111

LOW–VOLTAGE 1:10 DIFFERENTIAL ECL/PECL CLOCK DRIVER

Motorola => Freescale 

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Low-Voltage 1:10 Differential

ECL/PECL Clock Driver

MC100EP111

The MC100EP111 is a low skew 1–to–10 differential driver, designed

with clock distribution in mind. It accepts two clock sources into an input

multiplexer. The input signals can be either differential or single–ended if

the VBB output is used. The selected signal is fanned out to 10 identical

differential outputs.

• 100ps Part–to–Part Skew

• 35ps Output–to–Output Skew

• Differential Design

• VBB Output

• Voltage and Temperature Compensated Outputs

• Low Voltage VEE Range of –2.375 to –3.8V

• 75kΩ Input Pulldown Resistors

LOW–VOLTAGE

1:10 DIFFERENTIAL

ECL/PECL CLOCK DRIVER

The EP111 is specifically designed, modeled and produced with low

skew as the key goal. Optimal design and layout serve to minimize gate–

to–gate skew within a device, and empirical modeling is used to

determine process control limits that ensure consistent tpd distributions

from lot to lot. The net result is a dependable, guaranteed low skew

device.

To ensure that the tight skew specification is met it is necessary that

both sides of the differential output are terminated into 50Ω, even if only

one side is being used. In most applications, all ten differential pairs will

be used and therefore terminated. In the case where fewer than ten pairs

are used, it is necessary to terminate at least the output pairs on the same

package side as the pair(s) being used on that side, in order to maintain

minimum skew. Failure to do this will result in small degradations of

propagation delay (on the order of 10–20ps) of the output(s) being used

which, while not being catastrophic to most designs, will mean a loss of

skew margin.

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02

The MC100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows

the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the

EP111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or

Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL,

designers should refer to Motorola Application Note AN1406/D.

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

2/97

© Motorola, Inc. 1997

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