PA7572J-20 Ver la hoja de datos (PDF) - International Cmos Technology

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componentes Descripción

Fabricante

PA7572J-20

Programmable Electrically Erasable Logic Array

International Cmos Technology 

Commercial/Industrial

Table 4. A.C Electrical Characteristics Combinatorial

Symbol

Parameter6,12

tPDI

tPDX

tIA

tAL

tLC

tLO

tOD, tOE

tOX

Propagation delay Internal (tAL + tLC)

Propagation delay External (tIA + tAL +tLC + tLO)

Input or I/O pin to array input

Array input to LCC

LCC input to LCC output10

LCC output to output pin

Output Disable, Enable from LCC output7

Output Disable, Enable from input pin7

Over the Operating Range

-20/I-20

Min

Max

13

20

2

12

1

5

5

20

Unit

ns

ns

ns

ns

ns

ns

ns

ns

This device has been designed and tested for the recommended operating conditions. Proper operation outside of these

levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage

Figure 15. Combinatorial Timing - Waveforms and Block Diagram

7

04-02-050A

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