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NX25P10

1M-BIT, 2M-BIT AND 4M-BIT Serial Flash Memory with 40MHz SPI

NexFlash -> Winbond Electronics 

1M / 2M / 4M-BIT SERIAL FLASH MEMORY with 40MHz SPI

NX25P10, NX25P20 AND NX25P40

SPI OPERATION

SPI Modes

The NX25P10/20/40 is accessed through an SPI compat-

ible bus consisting of four signals: Serial Clock (CLK), Chip

Select (CS), Serial Data Input (DI) and Serial Data Output

(DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are

supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when

the SPI bus master is in standby and data is not being

transferred to the Serial Flash. For Mode 0 the CLK signal

is normally low. For Mode 3 the CLK signal is normally high.

In either case data input on the DI pin is sampled on the

rising edge of the CLK. Data output on the DO pin is clocked

out on the falling edge of CLK.

Hold Function

The HOLD signal allows the NX25P10/20/40 operation to be

paused while it is actively selected (when CS is low). The

hold function may be useful in cases where the SPI data and

clock signals are shared with other devices. For example,

consider if the page buffer was only partially written when a

priority interrupt requires use of the SPI bus. In this case the

hold function can save the state of the instruction and the

data in the buffer so programming can resume where it left

off once the bus is available again.

To initiate a hold condition, the device must be selected with

CS low. A hold condition will activate on the falling edge of

the HOLD signal if the CLK signal is already low. If the CLK

is not already low the hold condition will activate after the

next falling edge of CLK. The hold condition will terminate

on the rising edge of the hold signal if the CLK signal is

already low. If the CLK is not already low the hold condition

will terminate after the next falling edge of CLK.

During a hold condition, the Serial Data Output (DO) is high

impedance, and Serial Data Input (DI) and Serial Clock

(CLK) are ignored. The Chip Select (CS) signal should be

kept active (low) for the full duration of the hold operation to

avoid resetting the internal logic state of the device.

WRITE PROTECTION

Applications that use non-volatile memory must take into

consideration the possibility of noise and other adverse

system conditions that may compromise data integrity. To

address this concern the NX25P10/20/40 provides several

means to protect data from inadvertent writes.

Write Protect Features

• Device resets when Vcc is below threshold.

1

• Time delay write disable after Power-up.

• Write enable/disable instructions.

2

• Automatic write disable after program and erase.

• Software write protection using Status Register.

3 • Hardware write protection using Status Register and

WP pin.

• Write Protection using Power-down instruction.

4 Upon power-up or at power-down the NX25P10/20/40 will

maintain a reset condition while Vcc is below the threshold

value of VWI, (See Power-up Timing and Voltage Levels:

5 Table 7 and Figure 17). While reset, all operations are

disabled and no instructions are recognized. During power-

up and after the Vcc voltage exceeds VWI, all program and

erase related instructions are further disabled for a time

6 delay of tPUW. This includes the Write Enable, Page Pro-

gram, Sector Erase, Bulk Erase and the Write Status

Register instructions. Note that the chip select pin (CS)

must track the Vcc supply level at power-up until the Vcc-

min level and tVSL time delay is reached. If needed a pull-up

resister on CS can be used to accomplish this.

7

After power-up the device in automatically placed in a write-

disabled state with the Status Register Write Enable Latch

8 (WEL) set to a 0. A Write Enable instruction must be issued

before a Page Program, Sector Erase, Bulk Erase or Write

Status Register instruction will be accepted. After complet-

ing a program, erase or write instruction the Write Enable

9 Latch (WEL) is automatically cleared to a write-disabled state

of 0.

Software controlled write protection is facilitated using the

1 0 Write Status Register instruction and setting the Status

Register Protect (SRP) and Block Protect (BP0, BP2) bits.

These Status Register bits allow a portion or all of the

memory to be configured as read only. Used in conjunction

1 1 with the Write Protect (WP) pin, changes to the Status

Register can be enabled or disabled under hardware control.

See Status Register for further information.

1 2 Additionally, the Power-down instruction offers an extra

level of write protection as all instructions are ignored

except for the Release Power-down instruction.

NexFlash Technologies, Inc.

7

PRELIMINARY MKP-0009 Rev 6 NXSF040I-0405

04/04/05 ©

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