NID9N05ACL(2016) Ver la hoja de datos (PDF) - ON Semiconductor
Número de pieza
componentes Descripción
Fabricante
NID9N05ACL Datasheet PDF : 7 Pages
| |||
NID9N05ACL, NID9N05BCL
Power MOSFET
9.0 A, 52 V, N−Channel, Logic Level,
Clamped MOSFET w/ESD Protection
in a DPAK Package
Benefits
• High Energy Capability for Inductive Loads
• Low Switching Noise Generation
Features
• Diode Clamp Between Gate and Source
• ESD Protection − HBM 5000 V
• Active Over−Voltage Gate to Drain Clamp
• Scalable to Lower or Higher RDS(on)
• Internal Series Gate Resistance
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• Automotive and Industrial Markets:
Solenoid Drivers, Lamp Drivers, Small Motor Drivers
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage Internally Clamped
Gate−to−Source Voltage − Continuous
Drain Current − Continuous @ TA = 25°C
Drain Current − Single Pulse (tp = 10 ms)
Total Power Dissipation @ TA = 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 125°C
(VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V,
RG = 25 W)
Thermal Resistance, Junction−to−Case
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
VDSS
VGS
ID
IDM
PD
TJ, Tstg
EAS
RqJC
RqJA
RqJA
TL
52−59
V
±15
V
9.0
A
35
1.74
W
−55 to 175 °C
160
mJ
5.2
°C/W
72
100
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2).
2. When surface mounted to a FR4 board using minimum recommended pad
size, (Cu area 0.412 in2).
www.onsemi.com
VDSS
(Clamped)
52 V
RDS(ON) TYP
90 mW
ID MAX
(Limited)
9.0 A
Drain
(Pins 2, 4)
Gate
(Pin 1)
Overvoltage
Protection
RG
ESD Protection
MPWR
Source
(Pin 3)
MARKING
DIAGRAM
DPAK
CASE 369C
STYLE 2
1
YWW
2
D9N
4
xxxxxG
3
Y
WW
xxxxx
G
= Year
= Work Week
= 05ACL or 05BCL
= Pb−Free Package
1 = Gate
2 = Drain
3 = Source
4 = Drain
ORDERING INFORMATION
Device
Package
Shipping†
NID9N05ACLT4G DPAK 2500/Tape & Reel
(Pb−Free)
NID9N05BCLT4G DPAK 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
November, 2016 − Rev. 11
Publication Order Number:
NID9N05CL/D
Share Link: 