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CXA2610N Ver la hoja de datos (PDF) - Sony Semiconductor

Número de pieza
componentes Descripción
Fabricante
CXA2610N
Sony
Sony Semiconductor Sony
CXA2610N Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
CXA2610N
Description of Functions
(1) LD drive current value setting
The current controlled by the current setting pins IINR, IIN2 and IIN3 is output from the LD0 pin.
The current flowing to the LD0 pin can be set independently for IINR, IIN2 and IIN3 by CONTR, CONT2 and
CONT3.
(2) LD drive current forced OFF
Forced OFF is enabled by setting the ENABLE pin Low.
(3) Oscillation circuit
The oscillation circuit is turned ON forcibly by setting the OSCENA pin Low.
(OSCENA × CONTR × (CONT2 + CONT3))
The oscillation circuit is turned ON by setting the OSCENA pin High only for read.
(OSCENA × CONTR × CONT2 × CONT3)
(4) Oscillation frequency adjustment
The oscillation frequency can be varied by the external resistance value connected to the OSCFR pin.
(5) Oscillation level adjustment
The oscillation level initial value can be set by the external resistance value connected to the OSCGA pin.
The oscillation level can be adjusted by varying the IINR input current value.
In addition, the read block DC compensation current IR that flows when oscillation is OFF is independent of
the OSCGA pin external resistance value, and is constant.
Oscillator OFF
Initial setting
Level adjustment
For large OSCGA
external resistance
(Io 0mA)
For small OSCGA
external resistance
2IR
IO + 2 (IR – IO)
IR
IO
0
IINR input current [µA]
12
2k
OSCGA external resistance []
IO
IR < IO
IR > IO
IINR input current [µA]
OSCGA pin voltage
40
IO
×
[mAp-p]
OSCGA external resistance 9
(6) Logic
The logic table for the CONTR, CONT2, CONT3 and ENABLE pins is shown below.
Be sure to also check the timing chart on page 7.
ENABLE
L
H
H
H
H
H
CONTR
X
H
L
L
L
L
CONT2
X
H
H
L
H
L
CONT3
LD0
X
OFF
H
OFF
H
IINR
H
IINR + IIN2
L
IINR + IIN3
L
IINR + IIN2 + IIN3
–5–

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