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MK2732-05

Low Phase Noise VCXO+Multiplier

Integrated Circuit Systems 

MK2732-05

Low Phase Noise VCXO+Multiplier

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Minimum Typical Maximum Units

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5 V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

DC CHARACTERISTICS (VDD5 = 5.0V unless noted)

150

°C

Core Operating Voltage, VDD5

4.75

5.0

5.25

V

I/O Operating Voltage, VDDIO

3.15

3.3

VDD5

V

Input High Voltage, VIH, X1 pin only

3.5

2.5

V

Input Low Voltage, VIL, X1 pin only

2.5

1.5

V

Input High Voltage, VIH, binary inputs

S2, S1, OE

2

V

Input Low Voltage, VIL, binary inputs

S2, S1, OE

0.8

V

Input High Voltage, VIH, trinary input

S0, pin 10

VDDIO-0.5

V

Input Low Voltage, VIL, trinary input

S0, pin 10

0.5

V

Output High Voltage, VOH

IOH=-25mA

2.4

V

Output Low Voltage, VOL

IOL=25mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDDIO-0.4

V

Operating Supply Current, IDD

No Load

19

mA

Short Circuit Current

Each output

±100

mA

Input Capacitance

S2:S0, OE

7

pF

Frequency synthesis error

Both clocks

0

ppm

VIN, VCXO control voltage

0

AC CHARACTERISTICS (VDD5 = 5.0V unless noted)

3

V

Input Crystal Frequency

10

14.31818 MHz

Output Clock Frequency

2.5

85.9 MHz

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle

At VDDIO/2

40

60

%

Maximum Absolute Jitter

±100

ps

Phase Noise, relative to carrier

Output pullability, note 2

10 kHz offset

0V ≤ VIN ≤ 3V

-115

±100

dBc/Hz

ppm

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. With an ICS/MicroClock approved pullable crystal.

Pullable Crystal Specifications:

Correlation (load) Capacitance

CO/C1

ESR

Operating Temperature

Initial Accuracey

Temperature plus Aging Stability

14 pF

240 max

35 Ω max

0 to 70 °C

±20 ppm

±50 ppm

MDS 2732-05 D

3

Revision 122799

Printed 11/16/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126•(408) 295-9800 tel• www.icst.com

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