MB15F07SLPV Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Fabricante
MB15F07SLPV Datasheet PDF : 28 Pages
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MB15F07SL
s FUNCTIONAL DESCRIPTION
The VCO output frequency can be calculated using the following equation:
fVCO = {(M × N) + A} × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
M : Preset divide ratio of dual modulus prescaler (64 or 128 for PLL 1/PLL 2)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Reference oscillation frequency
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference
counters and the programmable counters separately.
Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the
shift register on the rising edge of the Clock. When the LE signal pin is taken high, entered data is latched into the
appropriate counters according to the control bit settings as follows:
Table 1. Control Bit
Control bit
CN1
CN2
L
L
H
L
L
H
H
H
Destination of serial data
The programmable reference counter for PLL 1
The programmable reference counter for PLL 2
The programmable counter and the swallow counter for PLL 1
The programmable counter and the swallow counter for PLL 2
Shift Register Configuration
Programmable Reference Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
RRRRRRC
9 10 11 12 13 14 S
X
X
X
X
CN1,2
R1 to R14
T1, 2
CS
X
: Control bits
[Table 1]
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2]
: Test purpose bits
[Table 3]
: Charge pump current select bit
[Table 9]
: Dummy bits (Set “0” or “1”)
NOTE: Input data with MSB first.
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