MB15F07SLPV Ver la hoja de datos (PDF) - Fujitsu

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componentes Descripción

Fabricante

MB15F07SLPV

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F07SL

s PIN DESCRIPTIONS

Pin no.

SSOP BCC

1

16

2

1

3

2

4

3

5

4

Pin

name

GND2

OSCIN

GND1

fin1

VCC1

6

5 LD/fout

7

6

PS1

8

7

Do1

9

8

Do2

10

9

PS2

11

10

Xfin2

12

11

VCC2

13

12

fin2

14

13

LE

15

14

Data

16

15 Clock

I/O

Descriptions

– Ground for PLL 2 section.

I

The programmable reference divider input. TCXO should be connected via

an AC coupling capacitor.

– Ground for the PLL 1 section.

I

Prescaler input pin for the PLL 1.

Connection to an external VCO should be via AC coupling.

– Power supply voltage input pin for the PLL 1 section.

Lock detect signal output (LD)/phase comparator monitoring

output (fout).

O The output signal is selected by LDS bit in the serial data.

LDS bit = “H” ; outputs fout signal

LDS bit = “L” ; outputs LD signal

Power saving mode control for the PLL 1 section. This pin must be set

I

at “L” during Power-ON. (Open is prohibited.)

PS1 = “H” ; Normal mode

PS1 = “L” ; Power saving mode

Charge pump output for the PLL 1 section.

O Phase characteristics of the phase detector can be selected via

programming of the FC-bit.

Charge pump output for the PLL 2 section.

O Phase characteristics of the phase detector can be selected via

programming of the FC-bit.

Power saving mode control for the PLL 2 section. This pin must be set

I

at “L” during Power-ON. (Open is prohibited.)

PS2 = “H” ; Normal mode

PS2 = “L” ; Power saving mode

I

Prescaler complementary input for the PLL 2 section.

This pin should be grounded via a capacitor.

–

Power supply voltage input pin for the PLL 2 section, the shift register and

the oscillator input buffer. When power is OFF, latched data of PLL 2 is lost.

I

Prescaler input pin for the PLL 2.

Connection to an external VCO should be via AC coupling.

Load enable signal inpunt (with a schmitt trigger input buffer.)

I When the LE bit is set “H”, data in the shift register is transferred to the

corresponding latch according to the control bit in the serial data.

Serial data input (with a schmitt trigger input buffer.)

I

Data is transferred to the corresponding latch (PLL 1-ref counter, PLL 1-

prog. counter, PLL 2-ref. counter, PLL 2-prog. counter) according to the

control bit in the serial data.

I

Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)

One bit of data is shifted into the shift register on a rising edge of the clock.

3

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