MB15F07SLPV Ver la hoja de datos (PDF) - Fujitsu

Número de pieza

componentes Descripción

Fabricante

MB15F07SLPV

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F07SL

Table 4. Binary 11-bit Programmable Counter Data Setting

Divide

ratio

(N)

NNNNNNNNNNN

11 10 9 8 7 6 5 4 3 2 1

3

00000000011

4

⋅

2047

00000000100

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

11111111111

Note: • Divide ratio less than 3 is prohibited.

Table 5. Binary 7-bit Swallow Counter Data Setting

Divide

ratio

(N)

AAAAAAA

7654321

0

0000000

1

0000001

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

127

1111111

Note: • Divide ratio (A) range = 0 to 127

Table 6. Prescaler Data Setting

SW = “H”

Prescaler

divide ratio

PLL 1

PLL 2

64/65

64/65

SW = “L”

128/129

128/129

Table 7. Phase Comparator Phase Switching Data Setting

FC1, 2 = “H”

FC1, 2 = “L”

Do1, 2

fr > fp

H

L

fr = fp

Z

Z

fr < fp

L

H

VCO Output

Frequency

VCO polarity

(1)

(2)

(1)

(2)

LPF Output Voltage

The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (DO)

is reversed according to the FC bit setting. The relationship between the FC bit setting and DO is shown above.

Z = High-impedance

10

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