MX29F1615 Ver la hoja de datos (PDF) - Macronix International
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MX29F1615 Datasheet PDF : 26 Pages
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MX29F1615
READ/RESET COMMAND
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until the
CIR contents are altered by a valid command sequence.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during
the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.
The MX29F1615 is accessed like an EPROM. When CE
and OE are low and BYTE/VPP is high or low the data
stored at the memory location determined by the address
pins is asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual line control gives designers flexibility in preventing
bus contention.
Note that the read/reset command is not valid when
program or erase is in progress.
PROGRAM
Any page to be programmed should have the page in the
erased state first, i.e. performing sector erase is
suggested before page programming can be performed.
The device is programmed on a page basis. If a word of
data within a page is to be changed, data for the entire page
can be loaded into the device. Any word that is not loaded
during the programming of its page will be still in the erased
state (i.e. FFH). Once the words of a page are loaded into
the device, they are simultaneously programmed during
the internal programming period. After the first data word
has been loaded into the device, successive words are
entered in the same manner. The time between word
loads must be less than 30us otherwise the load period
could be teminated. A6 to A19 specify the page address,
i.e., the device is page-aligned on 64 words boundary. The
page address must be valid during each high to low
transition of CE. A0 to A5 specify the byte address within
the page. The word may be loaded in any order; sequential
loading is not required. If a high to low transition of CE is
not detected whithin 100us of the last low to high transition,
the load period will end and the internal programming
period will start. The Auto page program terminates when
status on Q7 is '1' at which time the device stays at read
status register mode until the CIR contents are altered by
a valid command sequence.
PAGE PROGRAM
To initiate Page program mode, a three-cycle command
sequence is required. There are two " unlock" write cycles.
These are followed by writing the page program command-
A0H.
Any attempt to write to the device without the three-cycle
command sequence will not start the internal Write State
Machine(WSM), no data will be written to the device.
After three-cycle command sequence is given, a word load
is performed by applying a low pulse on the CE input with
CE low (respectively) and OE high. The address is latched
on the falling edge of CE, whichever occurs last. The data
is latched by the first rising edge of CE. Maximum of 64
words of data may be loaded into each page by the same
procedure as outlined in the page program section below.
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.
Chip erase does not require the user to program the
device prior to erase.
The automatic erase begins on the rising edge of the last
CE pulse in the command sequence and terminates when
the status on Q7 is "1" at which time the device stays at
read status register mode. The device remains enabled for
read status register mode until the CIR contents are
altered by a valid command sequence.
P/N: PM0615
REV. 1.1, JUN. 15, 2001
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