DT28F320J5-120 Ver la hoja de datos (PDF) - Intel
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DT28F320J5-120 Datasheet PDF : 51 Pages
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28F320J5 and 28F640J5
Revision History
Date of
Revision
09/01/97
09/17/97
12/01/97
01/31/98
03/23/98
07/13/98
12/01/98
05/04/99
09/16/99
10/20/99
11/08/99
12/16/99
06/26/00
03/28/01
04/23/02
Version
-001
-002
-003
-004
-005
-006
-007
-008
-009
-010
-011
-012
-013
-014
-015
Description
Original version
Modifications made to cover sheet
VCC/GND Pins Converted to No Connects Specification Change added
ICCS, ICCD, ICCW and ICCE Specification Change added
Order Codes Specification Change added
The µBGA* chip-scale package in Figure 2 was changed to a 52-ball package
and appropriate documentation added. The 64-Mb µBGA package dimensions
were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP.
32-Mbit Intel StrataFlash memory read access time added. The number of
block erase cycles was changed. The write buffer program time was changed.
The operating temperature was changed. A read parameter was added. Sev-
eral program, erase, and lock-bit specifications were changed. Minor docu-
mentation changes were made as well. Datasheet designation changed from
Advance Information to Preliminary.
Intel StrataFlash memory 32-Mbit µBGA package removed. tEHEL read specifi-
cation reduced. Table 4 was modified. The Ordering Information was updated.
Removed 32 Mbit, 100 ns references and ordering information for same. Pro-
vided clearer VOH specifications. Provided maximum program/erase specifica-
tion. Added Input Signal Transitions—Reducing Overshoots and Undershoots
When Using Buffers/Transceivers to Design Considerations section.
Name of document changed from Intel® StrataFlash™ Memory Technology 32
and 64 Mbit.
Updated CFI Tables, Section 4.2.1—Section 4.2.7.
Operating Temperature Range Specification was increased to –20 °C to
+85° C. The 32-Mbit Read Access at +85 °C was changed (Section 6.5, AC
Characteristics-Read Only Operations).
Modified Write Pulse Width definition
Added lock-bit default status (Section 4.11)
Added order code information for –20 °C to +85 °C
Modified Chip Enable Truth Table
Corrected error in command table
Removed erase queuing option from Figure 9, Block Erase Flowchart
Add reference to 0.25 micron process on cover page
Corrected error in Table 10, Maximum buffer write time.
Updated section 6.7 program/erase times.
Corrected error in table 19 maximum temperature range
Changed Clear Block-Lock Bit Time in Section 6.7.
Added .25 micron ETOX VI process technology ordering information
Removed µBGA CSP information
Datasheet
5
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