GS820E32AT-150 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS820E32AT-150

64K x 32 2M Synchronous Burst SRAM

Giga Semiconductor 

GS820E32AT/Q-150/138/133/117/100/66

Flow Through Read-Write Cycle Timing

Single Read

Single Write

Burst Read

CK

ADSP

tS tH

tKC

tKH tKL

ADSP is blocked by E inactive

tS tH ADSC initiated read

ADSC

tS tH

ADV

A0-An

GW

tS tH

RD1

tS tH

tS

WR1

RD2

tH

BW

BA - BD

E1

E2

E3

tS tH

tS tH

WR1

E1 masks ADSP

tS tH

E2 and E3 only sampled with ADSP and ADSC

tS tH

Deselected with E3

tOE tOHZ

G

DQA - DQD

tKQ

Hi-Z

Q1A

tS tH

D1A

Q2A

Q2B

Q2C Q2D Q2A

Burst wrap around to it’s initial state

Rev: 1.04 3/2000

16/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2000, Giga Semiconductor, Inc.

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